1 /**************************************************************************
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
31 * \file radeon_screen.c
32 * Screen initialization functions for the Radeon driver.
34 * \author Kevin E. Martin <martin@valinux.com>
35 * \author Gareth Hughes <gareth@valinux.com>
39 #include "main/glheader.h"
40 #include "main/imports.h"
41 #include "main/mtypes.h"
42 #include "main/framebuffer.h"
43 #include "main/renderbuffer.h"
45 #define STANDALONE_MMIO
46 #include "radeon_chipset.h"
47 #include "radeon_macros.h"
48 #include "radeon_screen.h"
49 #include "radeon_common.h"
50 #if defined(RADEON_R100)
51 #include "radeon_context.h"
52 #include "radeon_tex.h"
53 #elif defined(RADEON_R200)
54 #include "r200_context.h"
56 #elif defined(RADEON_R300)
57 #include "r300_context.h"
59 #elif defined(RADEON_R600)
60 #include "r600_context.h"
61 #include "r700_driconf.h" /* +r6/r7 */
62 #include "r600_tex.h" /* +r6/r7 */
68 #include "radeon_bocs_wrapper.h"
70 #include "GL/internal/dri_interface.h"
72 /* Radeon configuration
76 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
77 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
78 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
79 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
82 #if defined(RADEON_R100) /* R100 */
83 PUBLIC
const char __driConfigOptions
[] =
85 DRI_CONF_SECTION_PERFORMANCE
86 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
87 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
88 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
89 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
90 DRI_CONF_HYPERZ(false)
91 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
93 DRI_CONF_SECTION_QUALITY
94 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
95 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
96 DRI_CONF_NO_NEG_LOD_BIAS(false)
97 DRI_CONF_FORCE_S3TC_ENABLE(false)
98 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
99 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
100 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
101 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
103 DRI_CONF_SECTION_DEBUG
104 DRI_CONF_NO_RAST(false)
107 static const GLuint __driNConfigOptions
= 15;
109 #elif defined(RADEON_R200)
111 PUBLIC
const char __driConfigOptions
[] =
113 DRI_CONF_SECTION_PERFORMANCE
114 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
115 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
116 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
117 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
118 DRI_CONF_HYPERZ(false)
119 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
121 DRI_CONF_SECTION_QUALITY
122 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
123 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
124 DRI_CONF_NO_NEG_LOD_BIAS(false)
125 DRI_CONF_FORCE_S3TC_ENABLE(false)
126 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
127 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
128 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
129 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
130 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
132 DRI_CONF_SECTION_DEBUG
133 DRI_CONF_NO_RAST(false)
135 DRI_CONF_SECTION_SOFTWARE
136 DRI_CONF_NV_VERTEX_PROGRAM(false)
139 static const GLuint __driNConfigOptions
= 17;
141 #elif defined(RADEON_R300) || defined(RADEON_R600)
143 #define DRI_CONF_FP_OPTIMIZATION_SPEED 0
144 #define DRI_CONF_FP_OPTIMIZATION_QUALITY 1
146 /* TODO: integrate these into xmlpool.h! */
147 #define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
148 DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
149 DRI_CONF_DESC(en,"Number of texture image units") \
150 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
153 #define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
154 DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
155 DRI_CONF_DESC(en,"Number of texture coordinate units") \
156 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
161 #define DRI_CONF_DISABLE_S3TC(def) \
162 DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
163 DRI_CONF_DESC(en,"Disable S3TC compression") \
166 #define DRI_CONF_DISABLE_FALLBACK(def) \
167 DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
168 DRI_CONF_DESC(en,"Disable Low-impact fallback") \
171 #define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
172 DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
173 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
176 #define DRI_CONF_FP_OPTIMIZATION(def) \
177 DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
178 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
179 DRI_CONF_ENUM(0,"Optimize for Speed") \
180 DRI_CONF_ENUM(1,"Optimize for Quality") \
184 PUBLIC
const char __driConfigOptions
[] =
186 DRI_CONF_SECTION_PERFORMANCE
187 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN
)
188 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS
)
189 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0
)
190 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
191 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
192 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
193 DRI_CONF_DISABLE_FALLBACK(true)
194 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
196 DRI_CONF_SECTION_QUALITY
197 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB
)
198 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
199 DRI_CONF_FORCE_S3TC_ENABLE(false)
200 DRI_CONF_DISABLE_S3TC(false)
201 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER
)
202 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC
)
203 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF
)
204 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED
)
206 DRI_CONF_SECTION_DEBUG
207 DRI_CONF_NO_RAST(false)
210 static const GLuint __driNConfigOptions
= 17;
214 static int getSwapInfo( __DRIdrawable
*dPriv
, __DRIswapInfo
* sInfo
);
216 #ifndef RADEON_INFO_TILE_CONFIG
217 #define RADEON_INFO_TILE_CONFIG 0x6
221 radeonGetParam(__DRIscreen
*sPriv
, int param
, void *value
)
224 drm_radeon_getparam_t gp
= { 0 };
225 struct drm_radeon_info info
= { 0 };
227 if (sPriv
->drm_version
.major
>= 2) {
228 info
.value
= (uint64_t)(uintptr_t)value
;
230 case RADEON_PARAM_DEVICE_ID
:
231 info
.request
= RADEON_INFO_DEVICE_ID
;
233 case RADEON_PARAM_NUM_GB_PIPES
:
234 info
.request
= RADEON_INFO_NUM_GB_PIPES
;
236 case RADEON_PARAM_NUM_Z_PIPES
:
237 info
.request
= RADEON_INFO_NUM_Z_PIPES
;
239 case RADEON_INFO_TILE_CONFIG
:
240 info
.request
= RADEON_INFO_TILE_CONFIG
;
245 ret
= drmCommandWriteRead(sPriv
->fd
, DRM_RADEON_INFO
, &info
, sizeof(info
));
250 ret
= drmCommandWriteRead(sPriv
->fd
, DRM_RADEON_GETPARAM
, &gp
, sizeof(gp
));
255 static const __DRIconfig
**
256 radeonFillInModes( __DRIscreen
*psp
,
257 unsigned pixel_bits
, unsigned depth_bits
,
258 unsigned stencil_bits
, GLboolean have_back_buffer
)
260 __DRIconfig
**configs
;
262 unsigned depth_buffer_factor
;
263 unsigned back_buffer_factor
;
266 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
267 * enough to add support. Basically, if a context is created with an
268 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
269 * will never be used.
271 static const GLenum back_buffer_modes
[] = {
272 GLX_NONE
, GLX_SWAP_UNDEFINED_OML
/*, GLX_SWAP_COPY_OML */
275 uint8_t depth_bits_array
[2];
276 uint8_t stencil_bits_array
[2];
277 uint8_t msaa_samples_array
[1];
279 depth_bits_array
[0] = depth_bits
;
280 depth_bits_array
[1] = depth_bits
;
282 /* Just like with the accumulation buffer, always provide some modes
283 * with a stencil buffer. It will be a sw fallback, but some apps won't
286 stencil_bits_array
[0] = stencil_bits
;
287 stencil_bits_array
[1] = (stencil_bits
== 0) ? 8 : stencil_bits
;
289 msaa_samples_array
[0] = 0;
291 depth_buffer_factor
= (stencil_bits
== 0) ? 2 : 1;
292 back_buffer_factor
= (have_back_buffer
) ? 2 : 1;
294 if (pixel_bits
== 16) {
295 __DRIconfig
**configs_a8r8g8b8
;
296 __DRIconfig
**configs_r5g6b5
;
298 configs_r5g6b5
= driCreateConfigs(GL_RGB
, GL_UNSIGNED_SHORT_5_6_5
,
299 depth_bits_array
, stencil_bits_array
,
300 depth_buffer_factor
, back_buffer_modes
,
301 back_buffer_factor
, msaa_samples_array
,
303 configs_a8r8g8b8
= driCreateConfigs(GL_BGRA
, GL_UNSIGNED_INT_8_8_8_8_REV
,
304 depth_bits_array
, stencil_bits_array
,
305 1, back_buffer_modes
, 1,
306 msaa_samples_array
, 1, GL_TRUE
);
307 configs
= driConcatConfigs(configs_r5g6b5
, configs_a8r8g8b8
);
309 configs
= driCreateConfigs(GL_BGRA
, GL_UNSIGNED_INT_8_8_8_8_REV
,
310 depth_bits_array
, stencil_bits_array
,
312 back_buffer_modes
, back_buffer_factor
,
313 msaa_samples_array
, 1, GL_TRUE
);
315 if (configs
== NULL
) {
316 fprintf( stderr
, "[%s:%u] Error creating FBConfig!\n",
317 __func__
, __LINE__
);
321 /* Mark the visual as slow if there are "fake" stencil bits.
323 for (i
= 0; configs
[i
]; i
++) {
324 m
= &configs
[i
]->modes
;
325 if ((m
->stencilBits
!= 0) && (m
->stencilBits
!= stencil_bits
)) {
326 m
->visualRating
= GLX_SLOW_CONFIG
;
330 return (const __DRIconfig
**) configs
;
333 #if defined(RADEON_R100)
334 static const __DRItexOffsetExtension radeonTexOffsetExtension
= {
335 { __DRI_TEX_OFFSET
, __DRI_TEX_OFFSET_VERSION
},
339 static const __DRItexBufferExtension radeonTexBufferExtension
= {
340 { __DRI_TEX_BUFFER
, __DRI_TEX_BUFFER_VERSION
},
346 #if defined(RADEON_R200)
348 static const __DRItexOffsetExtension r200texOffsetExtension
= {
349 { __DRI_TEX_OFFSET
, __DRI_TEX_OFFSET_VERSION
},
353 static const __DRItexBufferExtension r200TexBufferExtension
= {
354 { __DRI_TEX_BUFFER
, __DRI_TEX_BUFFER_VERSION
},
360 #if defined(RADEON_R300)
361 static const __DRItexOffsetExtension r300texOffsetExtension
= {
362 { __DRI_TEX_OFFSET
, __DRI_TEX_OFFSET_VERSION
},
366 static const __DRItexBufferExtension r300TexBufferExtension
= {
367 { __DRI_TEX_BUFFER
, __DRI_TEX_BUFFER_VERSION
},
373 #if defined(RADEON_R600)
374 static const __DRItexOffsetExtension r600texOffsetExtension
= {
375 { __DRI_TEX_OFFSET
, __DRI_TEX_OFFSET_VERSION
},
376 r600SetTexOffset
, /* +r6/r7 */
379 static const __DRItexBufferExtension r600TexBufferExtension
= {
380 { __DRI_TEX_BUFFER
, __DRI_TEX_BUFFER_VERSION
},
381 r600SetTexBuffer
, /* +r6/r7 */
382 r600SetTexBuffer2
, /* +r6/r7 */
387 radeonDRI2Flush(__DRIdrawable
*drawable
)
389 radeonContextPtr rmesa
;
391 rmesa
= (radeonContextPtr
) drawable
->driContextPriv
->driverPrivate
;
392 radeonFlush(rmesa
->glCtx
);
395 static const struct __DRI2flushExtensionRec radeonFlushExtension
= {
396 { __DRI2_FLUSH
, __DRI2_FLUSH_VERSION
},
398 dri2InvalidateDrawable
,
401 static int radeon_set_screen_flags(radeonScreenPtr screen
, int device_id
)
403 screen
->device_id
= device_id
;
404 screen
->chip_flags
= 0;
405 switch ( device_id
) {
406 case PCI_CHIP_RN50_515E
:
407 case PCI_CHIP_RN50_5969
:
410 case PCI_CHIP_RADEON_LY
:
411 case PCI_CHIP_RADEON_LZ
:
412 case PCI_CHIP_RADEON_QY
:
413 case PCI_CHIP_RADEON_QZ
:
414 screen
->chip_family
= CHIP_FAMILY_RV100
;
417 case PCI_CHIP_RS100_4136
:
418 case PCI_CHIP_RS100_4336
:
419 screen
->chip_family
= CHIP_FAMILY_RS100
;
422 case PCI_CHIP_RS200_4137
:
423 case PCI_CHIP_RS200_4337
:
424 case PCI_CHIP_RS250_4237
:
425 case PCI_CHIP_RS250_4437
:
426 screen
->chip_family
= CHIP_FAMILY_RS200
;
429 case PCI_CHIP_RADEON_QD
:
430 case PCI_CHIP_RADEON_QE
:
431 case PCI_CHIP_RADEON_QF
:
432 case PCI_CHIP_RADEON_QG
:
433 /* all original radeons (7200) presumably have a stencil op bug */
434 screen
->chip_family
= CHIP_FAMILY_R100
;
435 screen
->chip_flags
= RADEON_CHIPSET_TCL
| RADEON_CHIPSET_BROKEN_STENCIL
;
438 case PCI_CHIP_RV200_QW
:
439 case PCI_CHIP_RV200_QX
:
440 case PCI_CHIP_RADEON_LW
:
441 case PCI_CHIP_RADEON_LX
:
442 screen
->chip_family
= CHIP_FAMILY_RV200
;
443 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
446 case PCI_CHIP_R200_BB
:
447 case PCI_CHIP_R200_BC
:
448 case PCI_CHIP_R200_QH
:
449 case PCI_CHIP_R200_QL
:
450 case PCI_CHIP_R200_QM
:
451 screen
->chip_family
= CHIP_FAMILY_R200
;
452 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
455 case PCI_CHIP_RV250_If
:
456 case PCI_CHIP_RV250_Ig
:
457 case PCI_CHIP_RV250_Ld
:
458 case PCI_CHIP_RV250_Lf
:
459 case PCI_CHIP_RV250_Lg
:
460 screen
->chip_family
= CHIP_FAMILY_RV250
;
461 screen
->chip_flags
= R200_CHIPSET_YCBCR_BROKEN
| RADEON_CHIPSET_TCL
;
464 case PCI_CHIP_RV280_5960
:
465 case PCI_CHIP_RV280_5961
:
466 case PCI_CHIP_RV280_5962
:
467 case PCI_CHIP_RV280_5964
:
468 case PCI_CHIP_RV280_5965
:
469 case PCI_CHIP_RV280_5C61
:
470 case PCI_CHIP_RV280_5C63
:
471 screen
->chip_family
= CHIP_FAMILY_RV280
;
472 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
475 case PCI_CHIP_RS300_5834
:
476 case PCI_CHIP_RS300_5835
:
477 case PCI_CHIP_RS350_7834
:
478 case PCI_CHIP_RS350_7835
:
479 screen
->chip_family
= CHIP_FAMILY_RS300
;
482 case PCI_CHIP_R300_AD
:
483 case PCI_CHIP_R300_AE
:
484 case PCI_CHIP_R300_AF
:
485 case PCI_CHIP_R300_AG
:
486 case PCI_CHIP_R300_ND
:
487 case PCI_CHIP_R300_NE
:
488 case PCI_CHIP_R300_NF
:
489 case PCI_CHIP_R300_NG
:
490 screen
->chip_family
= CHIP_FAMILY_R300
;
491 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
494 case PCI_CHIP_RV350_AP
:
495 case PCI_CHIP_RV350_AQ
:
496 case PCI_CHIP_RV350_AR
:
497 case PCI_CHIP_RV350_AS
:
498 case PCI_CHIP_RV350_AT
:
499 case PCI_CHIP_RV350_AV
:
500 case PCI_CHIP_RV350_AU
:
501 case PCI_CHIP_RV350_NP
:
502 case PCI_CHIP_RV350_NQ
:
503 case PCI_CHIP_RV350_NR
:
504 case PCI_CHIP_RV350_NS
:
505 case PCI_CHIP_RV350_NT
:
506 case PCI_CHIP_RV350_NV
:
507 screen
->chip_family
= CHIP_FAMILY_RV350
;
508 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
511 case PCI_CHIP_R350_AH
:
512 case PCI_CHIP_R350_AI
:
513 case PCI_CHIP_R350_AJ
:
514 case PCI_CHIP_R350_AK
:
515 case PCI_CHIP_R350_NH
:
516 case PCI_CHIP_R350_NI
:
517 case PCI_CHIP_R360_NJ
:
518 case PCI_CHIP_R350_NK
:
519 screen
->chip_family
= CHIP_FAMILY_R350
;
520 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
523 case PCI_CHIP_RV370_5460
:
524 case PCI_CHIP_RV370_5462
:
525 case PCI_CHIP_RV370_5464
:
526 case PCI_CHIP_RV370_5B60
:
527 case PCI_CHIP_RV370_5B62
:
528 case PCI_CHIP_RV370_5B63
:
529 case PCI_CHIP_RV370_5B64
:
530 case PCI_CHIP_RV370_5B65
:
531 case PCI_CHIP_RV380_3150
:
532 case PCI_CHIP_RV380_3152
:
533 case PCI_CHIP_RV380_3154
:
534 case PCI_CHIP_RV380_3155
:
535 case PCI_CHIP_RV380_3E50
:
536 case PCI_CHIP_RV380_3E54
:
537 screen
->chip_family
= CHIP_FAMILY_RV380
;
538 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
541 case PCI_CHIP_R420_JN
:
542 case PCI_CHIP_R420_JH
:
543 case PCI_CHIP_R420_JI
:
544 case PCI_CHIP_R420_JJ
:
545 case PCI_CHIP_R420_JK
:
546 case PCI_CHIP_R420_JL
:
547 case PCI_CHIP_R420_JM
:
548 case PCI_CHIP_R420_JO
:
549 case PCI_CHIP_R420_JP
:
550 case PCI_CHIP_R420_JT
:
551 case PCI_CHIP_R481_4B49
:
552 case PCI_CHIP_R481_4B4A
:
553 case PCI_CHIP_R481_4B4B
:
554 case PCI_CHIP_R481_4B4C
:
555 case PCI_CHIP_R423_UH
:
556 case PCI_CHIP_R423_UI
:
557 case PCI_CHIP_R423_UJ
:
558 case PCI_CHIP_R423_UK
:
559 case PCI_CHIP_R430_554C
:
560 case PCI_CHIP_R430_554D
:
561 case PCI_CHIP_R430_554E
:
562 case PCI_CHIP_R430_554F
:
563 case PCI_CHIP_R423_5550
:
564 case PCI_CHIP_R423_UQ
:
565 case PCI_CHIP_R423_UR
:
566 case PCI_CHIP_R423_UT
:
567 case PCI_CHIP_R430_5D48
:
568 case PCI_CHIP_R430_5D49
:
569 case PCI_CHIP_R430_5D4A
:
570 case PCI_CHIP_R480_5D4C
:
571 case PCI_CHIP_R480_5D4D
:
572 case PCI_CHIP_R480_5D4E
:
573 case PCI_CHIP_R480_5D4F
:
574 case PCI_CHIP_R480_5D50
:
575 case PCI_CHIP_R480_5D52
:
576 case PCI_CHIP_R423_5D57
:
577 screen
->chip_family
= CHIP_FAMILY_R420
;
578 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
581 case PCI_CHIP_RV410_5E4C
:
582 case PCI_CHIP_RV410_5E4F
:
583 case PCI_CHIP_RV410_564A
:
584 case PCI_CHIP_RV410_564B
:
585 case PCI_CHIP_RV410_564F
:
586 case PCI_CHIP_RV410_5652
:
587 case PCI_CHIP_RV410_5653
:
588 case PCI_CHIP_RV410_5657
:
589 case PCI_CHIP_RV410_5E48
:
590 case PCI_CHIP_RV410_5E4A
:
591 case PCI_CHIP_RV410_5E4B
:
592 case PCI_CHIP_RV410_5E4D
:
593 screen
->chip_family
= CHIP_FAMILY_RV410
;
594 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
597 case PCI_CHIP_RS480_5954
:
598 case PCI_CHIP_RS480_5955
:
599 case PCI_CHIP_RS482_5974
:
600 case PCI_CHIP_RS482_5975
:
601 case PCI_CHIP_RS400_5A41
:
602 case PCI_CHIP_RS400_5A42
:
603 case PCI_CHIP_RC410_5A61
:
604 case PCI_CHIP_RC410_5A62
:
605 screen
->chip_family
= CHIP_FAMILY_RS400
;
608 case PCI_CHIP_RS600_793F
:
609 case PCI_CHIP_RS600_7941
:
610 case PCI_CHIP_RS600_7942
:
611 screen
->chip_family
= CHIP_FAMILY_RS600
;
614 case PCI_CHIP_RS690_791E
:
615 case PCI_CHIP_RS690_791F
:
616 screen
->chip_family
= CHIP_FAMILY_RS690
;
618 case PCI_CHIP_RS740_796C
:
619 case PCI_CHIP_RS740_796D
:
620 case PCI_CHIP_RS740_796E
:
621 case PCI_CHIP_RS740_796F
:
622 screen
->chip_family
= CHIP_FAMILY_RS740
;
625 case PCI_CHIP_R520_7100
:
626 case PCI_CHIP_R520_7101
:
627 case PCI_CHIP_R520_7102
:
628 case PCI_CHIP_R520_7103
:
629 case PCI_CHIP_R520_7104
:
630 case PCI_CHIP_R520_7105
:
631 case PCI_CHIP_R520_7106
:
632 case PCI_CHIP_R520_7108
:
633 case PCI_CHIP_R520_7109
:
634 case PCI_CHIP_R520_710A
:
635 case PCI_CHIP_R520_710B
:
636 case PCI_CHIP_R520_710C
:
637 case PCI_CHIP_R520_710E
:
638 case PCI_CHIP_R520_710F
:
639 screen
->chip_family
= CHIP_FAMILY_R520
;
640 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
643 case PCI_CHIP_RV515_7140
:
644 case PCI_CHIP_RV515_7141
:
645 case PCI_CHIP_RV515_7142
:
646 case PCI_CHIP_RV515_7143
:
647 case PCI_CHIP_RV515_7144
:
648 case PCI_CHIP_RV515_7145
:
649 case PCI_CHIP_RV515_7146
:
650 case PCI_CHIP_RV515_7147
:
651 case PCI_CHIP_RV515_7149
:
652 case PCI_CHIP_RV515_714A
:
653 case PCI_CHIP_RV515_714B
:
654 case PCI_CHIP_RV515_714C
:
655 case PCI_CHIP_RV515_714D
:
656 case PCI_CHIP_RV515_714E
:
657 case PCI_CHIP_RV515_714F
:
658 case PCI_CHIP_RV515_7151
:
659 case PCI_CHIP_RV515_7152
:
660 case PCI_CHIP_RV515_7153
:
661 case PCI_CHIP_RV515_715E
:
662 case PCI_CHIP_RV515_715F
:
663 case PCI_CHIP_RV515_7180
:
664 case PCI_CHIP_RV515_7181
:
665 case PCI_CHIP_RV515_7183
:
666 case PCI_CHIP_RV515_7186
:
667 case PCI_CHIP_RV515_7187
:
668 case PCI_CHIP_RV515_7188
:
669 case PCI_CHIP_RV515_718A
:
670 case PCI_CHIP_RV515_718B
:
671 case PCI_CHIP_RV515_718C
:
672 case PCI_CHIP_RV515_718D
:
673 case PCI_CHIP_RV515_718F
:
674 case PCI_CHIP_RV515_7193
:
675 case PCI_CHIP_RV515_7196
:
676 case PCI_CHIP_RV515_719B
:
677 case PCI_CHIP_RV515_719F
:
678 case PCI_CHIP_RV515_7200
:
679 case PCI_CHIP_RV515_7210
:
680 case PCI_CHIP_RV515_7211
:
681 screen
->chip_family
= CHIP_FAMILY_RV515
;
682 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
685 case PCI_CHIP_RV530_71C0
:
686 case PCI_CHIP_RV530_71C1
:
687 case PCI_CHIP_RV530_71C2
:
688 case PCI_CHIP_RV530_71C3
:
689 case PCI_CHIP_RV530_71C4
:
690 case PCI_CHIP_RV530_71C5
:
691 case PCI_CHIP_RV530_71C6
:
692 case PCI_CHIP_RV530_71C7
:
693 case PCI_CHIP_RV530_71CD
:
694 case PCI_CHIP_RV530_71CE
:
695 case PCI_CHIP_RV530_71D2
:
696 case PCI_CHIP_RV530_71D4
:
697 case PCI_CHIP_RV530_71D5
:
698 case PCI_CHIP_RV530_71D6
:
699 case PCI_CHIP_RV530_71DA
:
700 case PCI_CHIP_RV530_71DE
:
701 screen
->chip_family
= CHIP_FAMILY_RV530
;
702 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
705 case PCI_CHIP_R580_7240
:
706 case PCI_CHIP_R580_7243
:
707 case PCI_CHIP_R580_7244
:
708 case PCI_CHIP_R580_7245
:
709 case PCI_CHIP_R580_7246
:
710 case PCI_CHIP_R580_7247
:
711 case PCI_CHIP_R580_7248
:
712 case PCI_CHIP_R580_7249
:
713 case PCI_CHIP_R580_724A
:
714 case PCI_CHIP_R580_724B
:
715 case PCI_CHIP_R580_724C
:
716 case PCI_CHIP_R580_724D
:
717 case PCI_CHIP_R580_724E
:
718 case PCI_CHIP_R580_724F
:
719 case PCI_CHIP_R580_7284
:
720 screen
->chip_family
= CHIP_FAMILY_R580
;
721 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
724 case PCI_CHIP_RV570_7280
:
725 case PCI_CHIP_RV560_7281
:
726 case PCI_CHIP_RV560_7283
:
727 case PCI_CHIP_RV560_7287
:
728 case PCI_CHIP_RV570_7288
:
729 case PCI_CHIP_RV570_7289
:
730 case PCI_CHIP_RV570_728B
:
731 case PCI_CHIP_RV570_728C
:
732 case PCI_CHIP_RV560_7290
:
733 case PCI_CHIP_RV560_7291
:
734 case PCI_CHIP_RV560_7293
:
735 case PCI_CHIP_RV560_7297
:
736 screen
->chip_family
= CHIP_FAMILY_RV560
;
737 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
740 case PCI_CHIP_R600_9400
:
741 case PCI_CHIP_R600_9401
:
742 case PCI_CHIP_R600_9402
:
743 case PCI_CHIP_R600_9403
:
744 case PCI_CHIP_R600_9405
:
745 case PCI_CHIP_R600_940A
:
746 case PCI_CHIP_R600_940B
:
747 case PCI_CHIP_R600_940F
:
748 screen
->chip_family
= CHIP_FAMILY_R600
;
749 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
752 case PCI_CHIP_RV610_94C0
:
753 case PCI_CHIP_RV610_94C1
:
754 case PCI_CHIP_RV610_94C3
:
755 case PCI_CHIP_RV610_94C4
:
756 case PCI_CHIP_RV610_94C5
:
757 case PCI_CHIP_RV610_94C6
:
758 case PCI_CHIP_RV610_94C7
:
759 case PCI_CHIP_RV610_94C8
:
760 case PCI_CHIP_RV610_94C9
:
761 case PCI_CHIP_RV610_94CB
:
762 case PCI_CHIP_RV610_94CC
:
763 case PCI_CHIP_RV610_94CD
:
764 screen
->chip_family
= CHIP_FAMILY_RV610
;
765 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
768 case PCI_CHIP_RV630_9580
:
769 case PCI_CHIP_RV630_9581
:
770 case PCI_CHIP_RV630_9583
:
771 case PCI_CHIP_RV630_9586
:
772 case PCI_CHIP_RV630_9587
:
773 case PCI_CHIP_RV630_9588
:
774 case PCI_CHIP_RV630_9589
:
775 case PCI_CHIP_RV630_958A
:
776 case PCI_CHIP_RV630_958B
:
777 case PCI_CHIP_RV630_958C
:
778 case PCI_CHIP_RV630_958D
:
779 case PCI_CHIP_RV630_958E
:
780 case PCI_CHIP_RV630_958F
:
781 screen
->chip_family
= CHIP_FAMILY_RV630
;
782 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
785 case PCI_CHIP_RV670_9500
:
786 case PCI_CHIP_RV670_9501
:
787 case PCI_CHIP_RV670_9504
:
788 case PCI_CHIP_RV670_9505
:
789 case PCI_CHIP_RV670_9506
:
790 case PCI_CHIP_RV670_9507
:
791 case PCI_CHIP_RV670_9508
:
792 case PCI_CHIP_RV670_9509
:
793 case PCI_CHIP_RV670_950F
:
794 case PCI_CHIP_RV670_9511
:
795 case PCI_CHIP_RV670_9515
:
796 case PCI_CHIP_RV670_9517
:
797 case PCI_CHIP_RV670_9519
:
798 screen
->chip_family
= CHIP_FAMILY_RV670
;
799 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
802 case PCI_CHIP_RV620_95C0
:
803 case PCI_CHIP_RV620_95C2
:
804 case PCI_CHIP_RV620_95C4
:
805 case PCI_CHIP_RV620_95C5
:
806 case PCI_CHIP_RV620_95C6
:
807 case PCI_CHIP_RV620_95C7
:
808 case PCI_CHIP_RV620_95C9
:
809 case PCI_CHIP_RV620_95CC
:
810 case PCI_CHIP_RV620_95CD
:
811 case PCI_CHIP_RV620_95CE
:
812 case PCI_CHIP_RV620_95CF
:
813 screen
->chip_family
= CHIP_FAMILY_RV620
;
814 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
817 case PCI_CHIP_RV635_9590
:
818 case PCI_CHIP_RV635_9591
:
819 case PCI_CHIP_RV635_9593
:
820 case PCI_CHIP_RV635_9595
:
821 case PCI_CHIP_RV635_9596
:
822 case PCI_CHIP_RV635_9597
:
823 case PCI_CHIP_RV635_9598
:
824 case PCI_CHIP_RV635_9599
:
825 case PCI_CHIP_RV635_959B
:
826 screen
->chip_family
= CHIP_FAMILY_RV635
;
827 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
830 case PCI_CHIP_RS780_9610
:
831 case PCI_CHIP_RS780_9611
:
832 case PCI_CHIP_RS780_9612
:
833 case PCI_CHIP_RS780_9613
:
834 case PCI_CHIP_RS780_9614
:
835 case PCI_CHIP_RS780_9615
:
836 case PCI_CHIP_RS780_9616
:
837 screen
->chip_family
= CHIP_FAMILY_RS780
;
838 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
840 case PCI_CHIP_RS880_9710
:
841 case PCI_CHIP_RS880_9711
:
842 case PCI_CHIP_RS880_9712
:
843 case PCI_CHIP_RS880_9713
:
844 case PCI_CHIP_RS880_9714
:
845 case PCI_CHIP_RS880_9715
:
846 screen
->chip_family
= CHIP_FAMILY_RS880
;
847 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
850 case PCI_CHIP_RV770_9440
:
851 case PCI_CHIP_RV770_9441
:
852 case PCI_CHIP_RV770_9442
:
853 case PCI_CHIP_RV770_9443
:
854 case PCI_CHIP_RV770_9444
:
855 case PCI_CHIP_RV770_9446
:
856 case PCI_CHIP_RV770_944A
:
857 case PCI_CHIP_RV770_944B
:
858 case PCI_CHIP_RV770_944C
:
859 case PCI_CHIP_RV770_944E
:
860 case PCI_CHIP_RV770_9450
:
861 case PCI_CHIP_RV770_9452
:
862 case PCI_CHIP_RV770_9456
:
863 case PCI_CHIP_RV770_945A
:
864 case PCI_CHIP_RV770_945B
:
865 case PCI_CHIP_RV770_945E
:
866 case PCI_CHIP_RV790_9460
:
867 case PCI_CHIP_RV790_9462
:
868 case PCI_CHIP_RV770_946A
:
869 case PCI_CHIP_RV770_946B
:
870 case PCI_CHIP_RV770_947A
:
871 case PCI_CHIP_RV770_947B
:
872 screen
->chip_family
= CHIP_FAMILY_RV770
;
873 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
876 case PCI_CHIP_RV730_9480
:
877 case PCI_CHIP_RV730_9487
:
878 case PCI_CHIP_RV730_9488
:
879 case PCI_CHIP_RV730_9489
:
880 case PCI_CHIP_RV730_948A
:
881 case PCI_CHIP_RV730_948F
:
882 case PCI_CHIP_RV730_9490
:
883 case PCI_CHIP_RV730_9491
:
884 case PCI_CHIP_RV730_9495
:
885 case PCI_CHIP_RV730_9498
:
886 case PCI_CHIP_RV730_949C
:
887 case PCI_CHIP_RV730_949E
:
888 case PCI_CHIP_RV730_949F
:
889 screen
->chip_family
= CHIP_FAMILY_RV730
;
890 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
893 case PCI_CHIP_RV710_9540
:
894 case PCI_CHIP_RV710_9541
:
895 case PCI_CHIP_RV710_9542
:
896 case PCI_CHIP_RV710_954E
:
897 case PCI_CHIP_RV710_954F
:
898 case PCI_CHIP_RV710_9552
:
899 case PCI_CHIP_RV710_9553
:
900 case PCI_CHIP_RV710_9555
:
901 case PCI_CHIP_RV710_9557
:
902 case PCI_CHIP_RV710_955F
:
903 screen
->chip_family
= CHIP_FAMILY_RV710
;
904 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
907 case PCI_CHIP_RV740_94A0
:
908 case PCI_CHIP_RV740_94A1
:
909 case PCI_CHIP_RV740_94A3
:
910 case PCI_CHIP_RV740_94B1
:
911 case PCI_CHIP_RV740_94B3
:
912 case PCI_CHIP_RV740_94B4
:
913 case PCI_CHIP_RV740_94B5
:
914 case PCI_CHIP_RV740_94B9
:
915 screen
->chip_family
= CHIP_FAMILY_RV740
;
916 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
919 case PCI_CHIP_CEDAR_68E0
:
920 case PCI_CHIP_CEDAR_68E1
:
921 case PCI_CHIP_CEDAR_68E4
:
922 case PCI_CHIP_CEDAR_68E5
:
923 case PCI_CHIP_CEDAR_68E8
:
924 case PCI_CHIP_CEDAR_68E9
:
925 case PCI_CHIP_CEDAR_68F1
:
926 case PCI_CHIP_CEDAR_68F8
:
927 case PCI_CHIP_CEDAR_68F9
:
928 case PCI_CHIP_CEDAR_68FE
:
929 screen
->chip_family
= CHIP_FAMILY_CEDAR
;
930 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
933 case PCI_CHIP_REDWOOD_68C0
:
934 case PCI_CHIP_REDWOOD_68C1
:
935 case PCI_CHIP_REDWOOD_68C8
:
936 case PCI_CHIP_REDWOOD_68C9
:
937 case PCI_CHIP_REDWOOD_68D8
:
938 case PCI_CHIP_REDWOOD_68D9
:
939 case PCI_CHIP_REDWOOD_68DA
:
940 case PCI_CHIP_REDWOOD_68DE
:
941 screen
->chip_family
= CHIP_FAMILY_REDWOOD
;
942 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
945 case PCI_CHIP_JUNIPER_68A0
:
946 case PCI_CHIP_JUNIPER_68A1
:
947 case PCI_CHIP_JUNIPER_68A8
:
948 case PCI_CHIP_JUNIPER_68A9
:
949 case PCI_CHIP_JUNIPER_68B0
:
950 case PCI_CHIP_JUNIPER_68B8
:
951 case PCI_CHIP_JUNIPER_68B9
:
952 case PCI_CHIP_JUNIPER_68BE
:
953 screen
->chip_family
= CHIP_FAMILY_JUNIPER
;
954 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
957 case PCI_CHIP_CYPRESS_6880
:
958 case PCI_CHIP_CYPRESS_6888
:
959 case PCI_CHIP_CYPRESS_6889
:
960 case PCI_CHIP_CYPRESS_688A
:
961 case PCI_CHIP_CYPRESS_6898
:
962 case PCI_CHIP_CYPRESS_6899
:
963 case PCI_CHIP_CYPRESS_689E
:
964 screen
->chip_family
= CHIP_FAMILY_CYPRESS
;
965 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
968 case PCI_CHIP_HEMLOCK_689C
:
969 case PCI_CHIP_HEMLOCK_689D
:
970 screen
->chip_family
= CHIP_FAMILY_HEMLOCK
;
971 screen
->chip_flags
= RADEON_CHIPSET_TCL
;
975 fprintf(stderr
, "unknown chip id 0x%x, can't guess.\n",
984 /* Create the device specific screen private data struct.
986 static radeonScreenPtr
987 radeonCreateScreen( __DRIscreen
*sPriv
)
989 radeonScreenPtr screen
;
990 RADEONDRIPtr dri_priv
= (RADEONDRIPtr
)sPriv
->pDevPriv
;
991 unsigned char *RADEONMMIO
= NULL
;
996 if (sPriv
->devPrivSize
!= sizeof(RADEONDRIRec
)) {
997 fprintf(stderr
,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
1001 /* Allocate the private area */
1002 screen
= (radeonScreenPtr
) CALLOC( sizeof(*screen
) );
1004 __driUtilMessage("%s: Could not allocate memory for screen structure",
1009 radeon_init_debug();
1011 /* parse information in __driConfigOptions */
1012 driParseOptionInfo (&screen
->optionCache
,
1013 __driConfigOptions
, __driNConfigOptions
);
1015 /* This is first since which regions we map depends on whether or
1016 * not we are using a PCI card.
1018 screen
->card_type
= (dri_priv
->IsPCI
? RADEON_CARD_PCI
: RADEON_CARD_AGP
);
1022 ret
= radeonGetParam(sPriv
, RADEON_PARAM_GART_BUFFER_OFFSET
,
1023 &screen
->gart_buffer_offset
);
1027 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret
);
1031 ret
= radeonGetParam(sPriv
, RADEON_PARAM_GART_BASE
,
1032 &screen
->gart_base
);
1035 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret
);
1039 ret
= radeonGetParam(sPriv
, RADEON_PARAM_IRQ_NR
,
1043 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret
);
1046 screen
->drmSupportsCubeMapsR200
= (sPriv
->drm_version
.minor
>= 7);
1047 screen
->drmSupportsBlendColor
= (sPriv
->drm_version
.minor
>= 11);
1048 screen
->drmSupportsTriPerf
= (sPriv
->drm_version
.minor
>= 16);
1049 screen
->drmSupportsFragShader
= (sPriv
->drm_version
.minor
>= 18);
1050 screen
->drmSupportsPointSprites
= (sPriv
->drm_version
.minor
>= 13);
1051 screen
->drmSupportsCubeMapsR100
= (sPriv
->drm_version
.minor
>= 15);
1052 screen
->drmSupportsVertexProgram
= (sPriv
->drm_version
.minor
>= 25);
1053 screen
->drmSupportsOcclusionQueries
= (sPriv
->drm_version
.minor
>= 30);
1056 ret
= radeon_set_screen_flags(screen
, dri_priv
->deviceID
);
1060 screen
->mmio
.handle
= dri_priv
->registerHandle
;
1061 screen
->mmio
.size
= dri_priv
->registerSize
;
1062 if ( drmMap( sPriv
->fd
,
1063 screen
->mmio
.handle
,
1065 &screen
->mmio
.map
) ) {
1067 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__
);
1071 RADEONMMIO
= screen
->mmio
.map
;
1073 screen
->status
.handle
= dri_priv
->statusHandle
;
1074 screen
->status
.size
= dri_priv
->statusSize
;
1075 if ( drmMap( sPriv
->fd
,
1076 screen
->status
.handle
,
1077 screen
->status
.size
,
1078 &screen
->status
.map
) ) {
1079 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
1081 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__
);
1084 if (screen
->chip_family
< CHIP_FAMILY_R600
)
1085 screen
->scratch
= (__volatile__
uint32_t *)
1086 ((GLubyte
*)screen
->status
.map
+ RADEON_SCRATCH_REG_OFFSET
);
1088 screen
->scratch
= (__volatile__
uint32_t *)
1089 ((GLubyte
*)screen
->status
.map
+ R600_SCRATCH_REG_OFFSET
);
1091 screen
->buffers
= drmMapBufs( sPriv
->fd
);
1092 if ( !screen
->buffers
) {
1093 drmUnmap( screen
->status
.map
, screen
->status
.size
);
1094 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
1096 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__
);
1100 if ( dri_priv
->gartTexHandle
&& dri_priv
->gartTexMapSize
) {
1101 screen
->gartTextures
.handle
= dri_priv
->gartTexHandle
;
1102 screen
->gartTextures
.size
= dri_priv
->gartTexMapSize
;
1103 if ( drmMap( sPriv
->fd
,
1104 screen
->gartTextures
.handle
,
1105 screen
->gartTextures
.size
,
1106 (drmAddressPtr
)&screen
->gartTextures
.map
) ) {
1107 drmUnmapBufs( screen
->buffers
);
1108 drmUnmap( screen
->status
.map
, screen
->status
.size
);
1109 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
1111 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__
);
1115 screen
->gart_texture_offset
= dri_priv
->gartTexOffset
+ screen
->gart_base
;
1118 if ((screen
->chip_family
== CHIP_FAMILY_R350
|| screen
->chip_family
== CHIP_FAMILY_R300
) &&
1119 sPriv
->ddx_version
.minor
< 2) {
1120 fprintf(stderr
, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
1124 if ((sPriv
->drm_version
.minor
< 29) && (screen
->chip_family
>= CHIP_FAMILY_RV515
)) {
1125 fprintf(stderr
, "R500 support requires a newer drm.\n");
1129 if (getenv("R300_NO_TCL"))
1130 screen
->chip_flags
&= ~RADEON_CHIPSET_TCL
;
1132 if (screen
->chip_family
<= CHIP_FAMILY_RS200
)
1133 screen
->chip_flags
|= RADEON_CLASS_R100
;
1134 else if (screen
->chip_family
<= CHIP_FAMILY_RV280
)
1135 screen
->chip_flags
|= RADEON_CLASS_R200
;
1136 else if (screen
->chip_family
<= CHIP_FAMILY_RV570
)
1137 screen
->chip_flags
|= RADEON_CLASS_R300
;
1139 screen
->chip_flags
|= RADEON_CLASS_R600
;
1141 screen
->cpp
= dri_priv
->bpp
/ 8;
1142 screen
->AGPMode
= dri_priv
->AGPMode
;
1144 ret
= radeonGetParam(sPriv
, RADEON_PARAM_FB_LOCATION
, &temp
);
1147 if(screen
->chip_family
>= CHIP_FAMILY_R600
)
1152 fprintf(stderr
, "Unable to get fb location need newer drm\n");
1157 screen
->fbLocation
= (temp
& 0xffff) << 24;
1164 if (screen
->chip_family
< CHIP_FAMILY_RS600
&& !screen
->kernel_mm
)
1165 screen
->fbLocation
= ( INREG( RADEON_MC_FB_LOCATION
) & 0xffff) << 16;
1169 fprintf(stderr
, "Unable to get fb location need newer drm\n");
1175 screen
->fbLocation
= (temp
& 0xffff) << 16;
1179 if (IS_R300_CLASS(screen
)) {
1180 ret
= radeonGetParam(sPriv
, RADEON_PARAM_NUM_GB_PIPES
, &temp
);
1182 fprintf(stderr
, "Unable to get num_pipes, need newer drm\n");
1183 switch (screen
->chip_family
) {
1184 case CHIP_FAMILY_R300
:
1185 case CHIP_FAMILY_R350
:
1186 screen
->num_gb_pipes
= 2;
1188 case CHIP_FAMILY_R420
:
1189 case CHIP_FAMILY_R520
:
1190 case CHIP_FAMILY_R580
:
1191 case CHIP_FAMILY_RV560
:
1192 case CHIP_FAMILY_RV570
:
1193 screen
->num_gb_pipes
= 4;
1195 case CHIP_FAMILY_RV350
:
1196 case CHIP_FAMILY_RV515
:
1197 case CHIP_FAMILY_RV530
:
1198 case CHIP_FAMILY_RV410
:
1200 screen
->num_gb_pipes
= 1;
1204 screen
->num_gb_pipes
= temp
;
1207 /* pipe overrides */
1208 switch (dri_priv
->deviceID
) {
1209 case PCI_CHIP_R300_AD
: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
1210 case PCI_CHIP_R350_AH
: /* 9800 SE only have 1 quadpipe */
1211 case PCI_CHIP_RV410_5E4C
: /* RV410 SE only have 1 quadpipe */
1212 case PCI_CHIP_RV410_5E4F
: /* RV410 SE only have 1 quadpipe */
1213 screen
->num_gb_pipes
= 1;
1219 if ( sPriv
->drm_version
.minor
>= 31 ) {
1220 ret
= radeonGetParam(sPriv
, RADEON_PARAM_NUM_Z_PIPES
, &temp
);
1222 screen
->num_z_pipes
= 2;
1224 screen
->num_z_pipes
= temp
;
1226 screen
->num_z_pipes
= 2;
1229 if ( sPriv
->drm_version
.minor
>= 10 ) {
1230 drm_radeon_setparam_t sp
;
1232 sp
.param
= RADEON_SETPARAM_FB_LOCATION
;
1233 sp
.value
= screen
->fbLocation
;
1235 drmCommandWrite( sPriv
->fd
, DRM_RADEON_SETPARAM
,
1236 &sp
, sizeof( sp
) );
1239 screen
->frontOffset
= dri_priv
->frontOffset
;
1240 screen
->frontPitch
= dri_priv
->frontPitch
;
1241 screen
->backOffset
= dri_priv
->backOffset
;
1242 screen
->backPitch
= dri_priv
->backPitch
;
1243 screen
->depthOffset
= dri_priv
->depthOffset
;
1244 screen
->depthPitch
= dri_priv
->depthPitch
;
1246 /* Check if ddx has set up a surface reg to cover depth buffer */
1247 screen
->depthHasSurface
= (sPriv
->ddx_version
.major
> 4) ||
1248 /* these chips don't use tiled z without hyperz. So always pretend
1249 we have set up a surface which will cause linear reads/writes */
1250 (IS_R100_CLASS(screen
) &&
1251 !(screen
->chip_flags
& RADEON_CHIPSET_TCL
));
1253 if ( dri_priv
->textureSize
== 0 ) {
1254 screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
] = screen
->gart_texture_offset
;
1255 screen
->texSize
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->gartTexMapSize
;
1256 screen
->logTexGranularity
[RADEON_LOCAL_TEX_HEAP
] =
1257 dri_priv
->log2GARTTexGran
;
1259 screen
->texOffset
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->textureOffset
1260 + screen
->fbLocation
;
1261 screen
->texSize
[RADEON_LOCAL_TEX_HEAP
] = dri_priv
->textureSize
;
1262 screen
->logTexGranularity
[RADEON_LOCAL_TEX_HEAP
] =
1263 dri_priv
->log2TexGran
;
1266 if ( !screen
->gartTextures
.map
|| dri_priv
->textureSize
== 0
1267 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
1268 screen
->numTexHeaps
= RADEON_NR_TEX_HEAPS
- 1;
1269 screen
->texOffset
[RADEON_GART_TEX_HEAP
] = 0;
1270 screen
->texSize
[RADEON_GART_TEX_HEAP
] = 0;
1271 screen
->logTexGranularity
[RADEON_GART_TEX_HEAP
] = 0;
1273 screen
->numTexHeaps
= RADEON_NR_TEX_HEAPS
;
1274 screen
->texOffset
[RADEON_GART_TEX_HEAP
] = screen
->gart_texture_offset
;
1275 screen
->texSize
[RADEON_GART_TEX_HEAP
] = dri_priv
->gartTexMapSize
;
1276 screen
->logTexGranularity
[RADEON_GART_TEX_HEAP
] =
1277 dri_priv
->log2GARTTexGran
;
1281 screen
->extensions
[i
++] = &driCopySubBufferExtension
.base
;
1282 screen
->extensions
[i
++] = &driReadDrawableExtension
;
1284 if ( screen
->irq
!= 0 ) {
1285 screen
->extensions
[i
++] = &driSwapControlExtension
.base
;
1286 screen
->extensions
[i
++] = &driMediaStreamCounterExtension
.base
;
1289 #if defined(RADEON_R100)
1290 screen
->extensions
[i
++] = &radeonTexOffsetExtension
.base
;
1293 #if defined(RADEON_R200)
1294 screen
->extensions
[i
++] = &r200texOffsetExtension
.base
;
1297 #if defined(RADEON_R300)
1298 screen
->extensions
[i
++] = &r300texOffsetExtension
.base
;
1301 #if defined(RADEON_R600)
1302 screen
->extensions
[i
++] = &r600texOffsetExtension
.base
;
1305 screen
->extensions
[i
++] = &dri2ConfigQueryExtension
.base
;
1307 screen
->extensions
[i
++] = NULL
;
1308 sPriv
->extensions
= screen
->extensions
;
1310 screen
->driScreen
= sPriv
;
1311 screen
->sarea_priv_offset
= dri_priv
->sarea_priv_offset
;
1312 screen
->sarea
= (drm_radeon_sarea_t
*) ((GLubyte
*) sPriv
->pSAREA
+
1313 screen
->sarea_priv_offset
);
1315 screen
->bom
= radeon_bo_manager_legacy_ctor(screen
);
1316 if (screen
->bom
== NULL
) {
1324 static radeonScreenPtr
1325 radeonCreateScreen2(__DRIscreen
*sPriv
)
1327 radeonScreenPtr screen
;
1330 uint32_t device_id
= 0;
1333 /* Allocate the private area */
1334 screen
= (radeonScreenPtr
) CALLOC( sizeof(*screen
) );
1336 __driUtilMessage("%s: Could not allocate memory for screen structure",
1338 fprintf(stderr
, "leaving here\n");
1342 radeon_init_debug();
1344 /* parse information in __driConfigOptions */
1345 driParseOptionInfo (&screen
->optionCache
,
1346 __driConfigOptions
, __driNConfigOptions
);
1348 screen
->kernel_mm
= 1;
1349 screen
->chip_flags
= 0;
1351 /* if we have kms we can support all of these */
1352 screen
->drmSupportsCubeMapsR200
= 1;
1353 screen
->drmSupportsBlendColor
= 1;
1354 screen
->drmSupportsTriPerf
= 1;
1355 screen
->drmSupportsFragShader
= 1;
1356 screen
->drmSupportsPointSprites
= 1;
1357 screen
->drmSupportsCubeMapsR100
= 1;
1358 screen
->drmSupportsVertexProgram
= 1;
1359 screen
->drmSupportsOcclusionQueries
= 1;
1362 ret
= radeonGetParam(sPriv
, RADEON_PARAM_DEVICE_ID
, &device_id
);
1365 fprintf(stderr
, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret
);
1369 ret
= radeon_set_screen_flags(screen
, device_id
);
1373 if (getenv("R300_NO_TCL"))
1374 screen
->chip_flags
&= ~RADEON_CHIPSET_TCL
;
1376 if (screen
->chip_family
<= CHIP_FAMILY_RS200
)
1377 screen
->chip_flags
|= RADEON_CLASS_R100
;
1378 else if (screen
->chip_family
<= CHIP_FAMILY_RV280
)
1379 screen
->chip_flags
|= RADEON_CLASS_R200
;
1380 else if (screen
->chip_family
<= CHIP_FAMILY_RV570
)
1381 screen
->chip_flags
|= RADEON_CLASS_R300
;
1383 screen
->chip_flags
|= RADEON_CLASS_R600
;
1386 if (IS_R600_CLASS(screen
) && (sPriv
->drm_version
.minor
>= 6)) {
1387 ret
= radeonGetParam(sPriv
, RADEON_INFO_TILE_CONFIG
, &temp
);
1389 fprintf(stderr
, "failed to get tiling info\n");
1391 screen
->tile_config
= temp
;
1392 screen
->r7xx_bank_op
= 0;
1393 switch((screen
->tile_config
& 0xe) >> 1) {
1395 screen
->num_channels
= 1;
1398 screen
->num_channels
= 2;
1401 screen
->num_channels
= 4;
1404 screen
->num_channels
= 8;
1407 fprintf(stderr
, "bad channels\n");
1410 switch((screen
->tile_config
& 0x30) >> 4) {
1412 screen
->num_banks
= 4;
1415 screen
->num_banks
= 8;
1418 fprintf(stderr
, "bad banks\n");
1421 switch((screen
->tile_config
& 0xc0) >> 6) {
1423 screen
->group_bytes
= 256;
1426 screen
->group_bytes
= 512;
1429 fprintf(stderr
, "bad group_bytes\n");
1435 if (IS_R300_CLASS(screen
)) {
1436 ret
= radeonGetParam(sPriv
, RADEON_PARAM_NUM_GB_PIPES
, &temp
);
1438 fprintf(stderr
, "Unable to get num_pipes, need newer drm\n");
1439 switch (screen
->chip_family
) {
1440 case CHIP_FAMILY_R300
:
1441 case CHIP_FAMILY_R350
:
1442 screen
->num_gb_pipes
= 2;
1444 case CHIP_FAMILY_R420
:
1445 case CHIP_FAMILY_R520
:
1446 case CHIP_FAMILY_R580
:
1447 case CHIP_FAMILY_RV560
:
1448 case CHIP_FAMILY_RV570
:
1449 screen
->num_gb_pipes
= 4;
1451 case CHIP_FAMILY_RV350
:
1452 case CHIP_FAMILY_RV515
:
1453 case CHIP_FAMILY_RV530
:
1454 case CHIP_FAMILY_RV410
:
1456 screen
->num_gb_pipes
= 1;
1460 screen
->num_gb_pipes
= temp
;
1463 /* pipe overrides */
1464 switch (device_id
) {
1465 case PCI_CHIP_R300_AD
: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
1466 case PCI_CHIP_R350_AH
: /* 9800 SE only have 1 quadpipe */
1467 case PCI_CHIP_RV410_5E4C
: /* RV410 SE only have 1 quadpipe */
1468 case PCI_CHIP_RV410_5E4F
: /* RV410 SE only have 1 quadpipe */
1469 screen
->num_gb_pipes
= 1;
1475 ret
= radeonGetParam(sPriv
, RADEON_PARAM_NUM_Z_PIPES
, &temp
);
1477 screen
->num_z_pipes
= 2;
1479 screen
->num_z_pipes
= temp
;
1484 screen
->extensions
[i
++] = &driCopySubBufferExtension
.base
;
1485 screen
->extensions
[i
++] = &driReadDrawableExtension
;
1486 screen
->extensions
[i
++] = &dri2ConfigQueryExtension
.base
;
1488 if ( screen
->irq
!= 0 ) {
1489 screen
->extensions
[i
++] = &driSwapControlExtension
.base
;
1490 screen
->extensions
[i
++] = &driMediaStreamCounterExtension
.base
;
1493 #if defined(RADEON_R100)
1494 screen
->extensions
[i
++] = &radeonTexBufferExtension
.base
;
1497 #if defined(RADEON_R200)
1498 screen
->extensions
[i
++] = &r200TexBufferExtension
.base
;
1501 #if defined(RADEON_R300)
1502 screen
->extensions
[i
++] = &r300TexBufferExtension
.base
;
1505 #if defined(RADEON_R600)
1506 screen
->extensions
[i
++] = &r600TexBufferExtension
.base
;
1509 screen
->extensions
[i
++] = &radeonFlushExtension
.base
;
1511 screen
->extensions
[i
++] = NULL
;
1512 sPriv
->extensions
= screen
->extensions
;
1514 screen
->driScreen
= sPriv
;
1515 screen
->bom
= radeon_bo_manager_gem_ctor(sPriv
->fd
);
1516 if (screen
->bom
== NULL
) {
1523 /* Destroy the device specific screen private data struct.
1526 radeonDestroyScreen( __DRIscreen
*sPriv
)
1528 radeonScreenPtr screen
= (radeonScreenPtr
)sPriv
->private;
1533 if (screen
->kernel_mm
) {
1534 #ifdef RADEON_BO_TRACK
1535 radeon_tracker_print(&screen
->bom
->tracker
, stderr
);
1537 radeon_bo_manager_gem_dtor(screen
->bom
);
1539 radeon_bo_manager_legacy_dtor(screen
->bom
);
1541 if ( screen
->gartTextures
.map
) {
1542 drmUnmap( screen
->gartTextures
.map
, screen
->gartTextures
.size
);
1544 drmUnmapBufs( screen
->buffers
);
1545 drmUnmap( screen
->status
.map
, screen
->status
.size
);
1546 drmUnmap( screen
->mmio
.map
, screen
->mmio
.size
);
1549 /* free all option information */
1550 driDestroyOptionInfo (&screen
->optionCache
);
1553 sPriv
->private = NULL
;
1557 /* Initialize the driver specific screen private data.
1560 radeonInitDriver( __DRIscreen
*sPriv
)
1562 if (sPriv
->dri2
.enabled
) {
1563 sPriv
->private = (void *) radeonCreateScreen2( sPriv
);
1565 sPriv
->private = (void *) radeonCreateScreen( sPriv
);
1567 if ( !sPriv
->private ) {
1568 radeonDestroyScreen( sPriv
);
1578 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
1580 * \todo This function (and its interface) will need to be updated to support
1584 radeonCreateBuffer( __DRIscreen
*driScrnPriv
,
1585 __DRIdrawable
*driDrawPriv
,
1586 const __GLcontextModes
*mesaVis
,
1587 GLboolean isPixmap
)
1589 radeonScreenPtr screen
= (radeonScreenPtr
) driScrnPriv
->private;
1591 const GLboolean swDepth
= GL_FALSE
;
1592 const GLboolean swAlpha
= GL_FALSE
;
1593 const GLboolean swAccum
= mesaVis
->accumRedBits
> 0;
1594 const GLboolean swStencil
= mesaVis
->stencilBits
> 0 &&
1595 mesaVis
->depthBits
!= 24;
1596 gl_format rgbFormat
;
1597 struct radeon_framebuffer
*rfb
;
1600 return GL_FALSE
; /* not implemented */
1602 rfb
= CALLOC_STRUCT(radeon_framebuffer
);
1606 _mesa_initialize_window_framebuffer(&rfb
->base
, mesaVis
);
1608 if (mesaVis
->redBits
== 5)
1609 rgbFormat
= _mesa_little_endian() ? MESA_FORMAT_RGB565
: MESA_FORMAT_RGB565_REV
;
1610 else if (mesaVis
->alphaBits
== 0)
1611 rgbFormat
= _mesa_little_endian() ? MESA_FORMAT_XRGB8888
: MESA_FORMAT_XRGB8888_REV
;
1613 rgbFormat
= _mesa_little_endian() ? MESA_FORMAT_ARGB8888
: MESA_FORMAT_ARGB8888_REV
;
1615 /* front color renderbuffer */
1616 rfb
->color_rb
[0] = radeon_create_renderbuffer(rgbFormat
, driDrawPriv
);
1617 _mesa_add_renderbuffer(&rfb
->base
, BUFFER_FRONT_LEFT
, &rfb
->color_rb
[0]->base
);
1618 rfb
->color_rb
[0]->has_surface
= 1;
1620 /* back color renderbuffer */
1621 if (mesaVis
->doubleBufferMode
) {
1622 rfb
->color_rb
[1] = radeon_create_renderbuffer(rgbFormat
, driDrawPriv
);
1623 _mesa_add_renderbuffer(&rfb
->base
, BUFFER_BACK_LEFT
, &rfb
->color_rb
[1]->base
);
1624 rfb
->color_rb
[1]->has_surface
= 1;
1627 if (mesaVis
->depthBits
== 24) {
1628 if (mesaVis
->stencilBits
== 8) {
1629 struct radeon_renderbuffer
*depthStencilRb
=
1630 radeon_create_renderbuffer(MESA_FORMAT_S8_Z24
, driDrawPriv
);
1631 _mesa_add_renderbuffer(&rfb
->base
, BUFFER_DEPTH
, &depthStencilRb
->base
);
1632 _mesa_add_renderbuffer(&rfb
->base
, BUFFER_STENCIL
, &depthStencilRb
->base
);
1633 depthStencilRb
->has_surface
= screen
->depthHasSurface
;
1635 /* depth renderbuffer */
1636 struct radeon_renderbuffer
*depth
=
1637 radeon_create_renderbuffer(MESA_FORMAT_X8_Z24
, driDrawPriv
);
1638 _mesa_add_renderbuffer(&rfb
->base
, BUFFER_DEPTH
, &depth
->base
);
1639 depth
->has_surface
= screen
->depthHasSurface
;
1641 } else if (mesaVis
->depthBits
== 16) {
1642 /* just 16-bit depth buffer, no hw stencil */
1643 struct radeon_renderbuffer
*depth
=
1644 radeon_create_renderbuffer(MESA_FORMAT_Z16
, driDrawPriv
);
1645 _mesa_add_renderbuffer(&rfb
->base
, BUFFER_DEPTH
, &depth
->base
);
1646 depth
->has_surface
= screen
->depthHasSurface
;
1649 _mesa_add_soft_renderbuffers(&rfb
->base
,
1650 GL_FALSE
, /* color */
1655 GL_FALSE
/* aux */);
1656 driDrawPriv
->driverPrivate
= (void *) rfb
;
1658 return (driDrawPriv
->driverPrivate
!= NULL
);
1662 static void radeon_cleanup_renderbuffers(struct radeon_framebuffer
*rfb
)
1664 struct radeon_renderbuffer
*rb
;
1666 rb
= rfb
->color_rb
[0];
1668 radeon_bo_unref(rb
->bo
);
1671 rb
= rfb
->color_rb
[1];
1673 radeon_bo_unref(rb
->bo
);
1676 rb
= radeon_get_renderbuffer(&rfb
->base
, BUFFER_DEPTH
);
1678 radeon_bo_unref(rb
->bo
);
1684 radeonDestroyBuffer(__DRIdrawable
*driDrawPriv
)
1686 struct radeon_framebuffer
*rfb
;
1690 rfb
= (void*)driDrawPriv
->driverPrivate
;
1693 radeon_cleanup_renderbuffers(rfb
);
1694 _mesa_reference_framebuffer((GLframebuffer
**)(&(driDrawPriv
->driverPrivate
)), NULL
);
1699 * This is the driver specific part of the createNewScreen entry point.
1701 * \todo maybe fold this into intelInitDriver
1703 * \return the __GLcontextModes supported by this driver
1705 static const __DRIconfig
**
1706 radeonInitScreen(__DRIscreen
*psp
)
1708 #if defined(RADEON_R100)
1709 static const char *driver_name
= "Radeon";
1710 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
1711 static const __DRIversion dri_expected
= { 4, 0, 0 };
1712 static const __DRIversion drm_expected
= { 1, 6, 0 };
1713 #elif defined(RADEON_R200)
1714 static const char *driver_name
= "R200";
1715 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
1716 static const __DRIversion dri_expected
= { 4, 0, 0 };
1717 static const __DRIversion drm_expected
= { 1, 6, 0 };
1718 #elif defined(RADEON_R300)
1719 static const char *driver_name
= "R300";
1720 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
1721 static const __DRIversion dri_expected
= { 4, 0, 0 };
1722 static const __DRIversion drm_expected
= { 1, 24, 0 };
1723 #elif defined(RADEON_R600)
1724 static const char *driver_name
= "R600";
1725 static const __DRIutilversion2 ddx_expected
= { 4, 5, 0, 0 };
1726 static const __DRIversion dri_expected
= { 4, 0, 0 };
1727 static const __DRIversion drm_expected
= { 1, 24, 0 };
1729 RADEONDRIPtr dri_priv
= (RADEONDRIPtr
) psp
->pDevPriv
;
1731 if ( ! driCheckDriDdxDrmVersions3( driver_name
,
1732 &psp
->dri_version
, & dri_expected
,
1733 &psp
->ddx_version
, & ddx_expected
,
1734 &psp
->drm_version
, & drm_expected
) ) {
1738 if (!radeonInitDriver(psp
))
1741 /* for now fill in all modes */
1742 return radeonFillInModes( psp
,
1744 (dri_priv
->bpp
== 16) ? 16 : 24,
1745 (dri_priv
->bpp
== 16) ? 0 : 8, 1);
1747 #define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0]))
1750 * This is the driver specific part of the createNewScreen entry point.
1751 * Called when using DRI2.
1753 * \return the __GLcontextModes supported by this driver
1756 __DRIconfig
**radeonInitScreen2(__DRIscreen
*psp
)
1758 GLenum fb_format
[3];
1760 /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't
1761 * support pageflipping at all.
1763 static const GLenum back_buffer_modes
[] = {
1764 GLX_NONE
, GLX_SWAP_UNDEFINED_OML
, /*, GLX_SWAP_COPY_OML*/
1766 uint8_t depth_bits
[4], stencil_bits
[4], msaa_samples_array
[1];
1768 __DRIconfig
**configs
= NULL
;
1770 if (!radeonInitDriver(psp
)) {
1774 stencil_bits
[0] = 0;
1776 stencil_bits
[1] = 0;
1778 stencil_bits
[2] = 0;
1780 stencil_bits
[3] = 8;
1782 msaa_samples_array
[0] = 0;
1784 fb_format
[0] = GL_RGB
;
1785 fb_type
[0] = GL_UNSIGNED_SHORT_5_6_5
;
1787 fb_format
[1] = GL_BGR
;
1788 fb_type
[1] = GL_UNSIGNED_INT_8_8_8_8_REV
;
1790 fb_format
[2] = GL_BGRA
;
1791 fb_type
[2] = GL_UNSIGNED_INT_8_8_8_8_REV
;
1793 for (color
= 0; color
< ARRAY_SIZE(fb_format
); color
++) {
1794 __DRIconfig
**new_configs
;
1796 new_configs
= driCreateConfigs(fb_format
[color
], fb_type
[color
],
1799 ARRAY_SIZE(depth_bits
),
1801 ARRAY_SIZE(back_buffer_modes
),
1803 ARRAY_SIZE(msaa_samples_array
),
1805 if (configs
== NULL
)
1806 configs
= new_configs
;
1808 configs
= driConcatConfigs(configs
, new_configs
);
1811 if (configs
== NULL
) {
1812 fprintf(stderr
, "[%s:%u] Error creating FBConfig!\n", __func__
,
1817 return (const __DRIconfig
**)configs
;
1821 * Get information about previous buffer swaps.
1824 getSwapInfo( __DRIdrawable
*dPriv
, __DRIswapInfo
* sInfo
)
1826 struct radeon_framebuffer
*rfb
;
1828 if ( (dPriv
== NULL
) || (dPriv
->driContextPriv
== NULL
)
1829 || (dPriv
->driContextPriv
->driverPrivate
== NULL
)
1830 || (sInfo
== NULL
) ) {
1834 rfb
= dPriv
->driverPrivate
;
1835 sInfo
->swap_count
= rfb
->swap_count
;
1836 sInfo
->swap_ust
= rfb
->swap_ust
;
1837 sInfo
->swap_missed_count
= rfb
->swap_missed_count
;
1839 sInfo
->swap_missed_usage
= (sInfo
->swap_missed_count
!= 0)
1840 ? driCalculateSwapUsage( dPriv
, 0, rfb
->swap_missed_ust
)
1846 const struct __DriverAPIRec driDriverAPI
= {
1847 .InitScreen
= radeonInitScreen
,
1848 .DestroyScreen
= radeonDestroyScreen
,
1849 #if defined(RADEON_R200)
1850 .CreateContext
= r200CreateContext
,
1851 .DestroyContext
= r200DestroyContext
,
1852 #elif defined(RADEON_R600)
1853 .CreateContext
= r600CreateContext
,
1854 .DestroyContext
= radeonDestroyContext
,
1855 #elif defined(RADEON_R300)
1856 .CreateContext
= r300CreateContext
,
1857 .DestroyContext
= radeonDestroyContext
,
1859 .CreateContext
= r100CreateContext
,
1860 .DestroyContext
= radeonDestroyContext
,
1862 .CreateBuffer
= radeonCreateBuffer
,
1863 .DestroyBuffer
= radeonDestroyBuffer
,
1864 .SwapBuffers
= radeonSwapBuffers
,
1865 .MakeCurrent
= radeonMakeCurrent
,
1866 .UnbindContext
= radeonUnbindContext
,
1867 .GetSwapInfo
= getSwapInfo
,
1868 .GetDrawableMSC
= driDrawableGetMSC32
,
1869 .WaitForMSC
= driWaitForMSC32
,
1871 .SwapBuffersMSC
= NULL
,
1872 .CopySubBuffer
= radeonCopySubBuffer
,
1874 .InitScreen2
= radeonInitScreen2
,
1877 /* This is the table of extensions that the loader will dlsym() for. */
1878 PUBLIC
const __DRIextension
*__driDriverExtensions
[] = {
1879 &driCoreExtension
.base
,
1880 &driLegacyExtension
.base
,
1881 &driDRI2Extension
.base
,