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r200: Prevent flush in middle of rendering.
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_screen.c
1 /**************************************************************************
2
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
5
6 All Rights Reserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /**
31 * \file radeon_screen.c
32 * Screen initialization functions for the Radeon driver.
33 *
34 * \author Kevin E. Martin <martin@valinux.com>
35 * \author Gareth Hughes <gareth@valinux.com>
36 */
37
38 #include <errno.h>
39 #include "main/glheader.h"
40 #include "main/imports.h"
41 #include "main/mtypes.h"
42 #include "main/framebuffer.h"
43 #include "main/renderbuffer.h"
44
45 #define STANDALONE_MMIO
46 #include "radeon_chipset.h"
47 #include "radeon_macros.h"
48 #include "radeon_screen.h"
49 #include "radeon_common.h"
50 #include "radeon_span.h"
51 #if !RADEON_COMMON
52 #include "radeon_context.h"
53 #include "radeon_tex.h"
54 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
55 #include "r200_context.h"
56 #include "r200_ioctl.h"
57 #include "r200_tex.h"
58 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
59 #include "r300_context.h"
60 #include "r300_tex.h"
61 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
62 #include "r600_context.h"
63 #include "r700_driconf.h" /* +r6/r7 */
64 #include "r600_tex.h" /* +r6/r7 */
65 #endif
66
67 #include "utils.h"
68 #include "vblank.h"
69 #include "drirenderbuffer.h"
70
71 #include "radeon_bocs_wrapper.h"
72
73 #include "GL/internal/dri_interface.h"
74
75 /* Radeon configuration
76 */
77 #include "xmlpool.h"
78
79 #define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
80 DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
81 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
82 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
83 DRI_CONF_OPT_END
84
85 #if !RADEON_COMMON /* R100 */
86 PUBLIC const char __driConfigOptions[] =
87 DRI_CONF_BEGIN
88 DRI_CONF_SECTION_PERFORMANCE
89 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
90 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
91 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
92 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
93 DRI_CONF_HYPERZ(false)
94 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
95 DRI_CONF_SECTION_END
96 DRI_CONF_SECTION_QUALITY
97 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
98 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
99 DRI_CONF_NO_NEG_LOD_BIAS(false)
100 DRI_CONF_FORCE_S3TC_ENABLE(false)
101 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
102 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
103 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
104 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
105 DRI_CONF_SECTION_END
106 DRI_CONF_SECTION_DEBUG
107 DRI_CONF_NO_RAST(false)
108 DRI_CONF_SECTION_END
109 DRI_CONF_END;
110 static const GLuint __driNConfigOptions = 15;
111
112 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
113
114 PUBLIC const char __driConfigOptions[] =
115 DRI_CONF_BEGIN
116 DRI_CONF_SECTION_PERFORMANCE
117 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
118 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
119 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
120 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
121 DRI_CONF_HYPERZ(false)
122 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
123 DRI_CONF_SECTION_END
124 DRI_CONF_SECTION_QUALITY
125 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
126 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
127 DRI_CONF_NO_NEG_LOD_BIAS(false)
128 DRI_CONF_FORCE_S3TC_ENABLE(false)
129 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
130 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
131 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
132 DRI_CONF_ALLOW_LARGE_TEXTURES(2)
133 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
134 DRI_CONF_SECTION_END
135 DRI_CONF_SECTION_DEBUG
136 DRI_CONF_NO_RAST(false)
137 DRI_CONF_SECTION_END
138 DRI_CONF_SECTION_SOFTWARE
139 DRI_CONF_NV_VERTEX_PROGRAM(false)
140 DRI_CONF_SECTION_END
141 DRI_CONF_END;
142 static const GLuint __driNConfigOptions = 17;
143
144 extern const struct dri_extension blend_extensions[];
145 extern const struct dri_extension ARB_vp_extension[];
146 extern const struct dri_extension NV_vp_extension[];
147 extern const struct dri_extension ATI_fs_extension[];
148 extern const struct dri_extension point_extensions[];
149
150 #elif RADEON_COMMON && (defined(RADEON_COMMON_FOR_R300) || defined(RADEON_COMMON_FOR_R600))
151
152 #define DRI_CONF_FP_OPTIMIZATION_SPEED 0
153 #define DRI_CONF_FP_OPTIMIZATION_QUALITY 1
154
155 /* TODO: integrate these into xmlpool.h! */
156 #define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
157 DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
158 DRI_CONF_DESC(en,"Number of texture image units") \
159 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
160 DRI_CONF_OPT_END
161
162 #define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
163 DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
164 DRI_CONF_DESC(en,"Number of texture coordinate units") \
165 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
166 DRI_CONF_OPT_END
167
168
169
170 #define DRI_CONF_DISABLE_S3TC(def) \
171 DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
172 DRI_CONF_DESC(en,"Disable S3TC compression") \
173 DRI_CONF_OPT_END
174
175 #define DRI_CONF_DISABLE_FALLBACK(def) \
176 DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
177 DRI_CONF_DESC(en,"Disable Low-impact fallback") \
178 DRI_CONF_OPT_END
179
180 #define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
181 DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
182 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
183 DRI_CONF_OPT_END
184
185 #define DRI_CONF_FP_OPTIMIZATION(def) \
186 DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
187 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
188 DRI_CONF_ENUM(0,"Optimize for Speed") \
189 DRI_CONF_ENUM(1,"Optimize for Quality") \
190 DRI_CONF_DESC_END \
191 DRI_CONF_OPT_END
192
193 PUBLIC const char __driConfigOptions[] =
194 DRI_CONF_BEGIN
195 DRI_CONF_SECTION_PERFORMANCE
196 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
197 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
198 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
199 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
200 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
201 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
202 DRI_CONF_DISABLE_FALLBACK(true)
203 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
204 DRI_CONF_SECTION_END
205 DRI_CONF_SECTION_QUALITY
206 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
207 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
208 DRI_CONF_FORCE_S3TC_ENABLE(false)
209 DRI_CONF_DISABLE_S3TC(false)
210 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
211 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
212 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
213 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED)
214 DRI_CONF_SECTION_END
215 DRI_CONF_SECTION_DEBUG
216 DRI_CONF_NO_RAST(false)
217 DRI_CONF_SECTION_END
218 DRI_CONF_END;
219 static const GLuint __driNConfigOptions = 17;
220
221 extern const struct dri_extension gl_20_extension[];
222
223 #ifndef RADEON_DEBUG
224
225 static const struct dri_debug_control debug_control[] = {
226 {"fall", DEBUG_FALLBACKS},
227 {"tex", DEBUG_TEXTURE},
228 {"ioctl", DEBUG_IOCTL},
229 {"prim", DEBUG_PRIMS},
230 {"vert", DEBUG_VERTS},
231 {"state", DEBUG_STATE},
232 {"code", DEBUG_CODEGEN},
233 {"vfmt", DEBUG_VFMT},
234 {"vtxf", DEBUG_VFMT},
235 {"verb", DEBUG_VERBOSE},
236 {"dri", DEBUG_DRI},
237 {"dma", DEBUG_DMA},
238 {"san", DEBUG_SANITY},
239 {"sync", DEBUG_SYNC},
240 {"pix", DEBUG_PIXEL},
241 {"mem", DEBUG_MEMORY},
242 {"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */
243 {NULL, 0}
244 };
245 #endif /* RADEON_DEBUG */
246
247 #endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */
248
249 extern const struct dri_extension card_extensions[];
250 extern const struct dri_extension mm_extensions[];
251
252 static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo );
253
254 static int
255 radeonGetParam(__DRIscreenPrivate *sPriv, int param, void *value)
256 {
257 int ret;
258 drm_radeon_getparam_t gp = { 0 };
259 struct drm_radeon_info info = { 0 };
260
261 if (sPriv->drm_version.major >= 2) {
262 info.value = (uint64_t)value;
263 switch (param) {
264 case RADEON_PARAM_DEVICE_ID:
265 info.request = RADEON_INFO_DEVICE_ID;
266 break;
267 case RADEON_PARAM_NUM_GB_PIPES:
268 info.request = RADEON_INFO_NUM_GB_PIPES;
269 break;
270 default:
271 return -EINVAL;
272 }
273 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_INFO, &info, sizeof(info));
274 } else {
275 gp.param = param;
276 gp.value = value;
277
278 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp));
279 }
280 return ret;
281 }
282
283 static const __DRIconfig **
284 radeonFillInModes( __DRIscreenPrivate *psp,
285 unsigned pixel_bits, unsigned depth_bits,
286 unsigned stencil_bits, GLboolean have_back_buffer )
287 {
288 __DRIconfig **configs;
289 __GLcontextModes *m;
290 unsigned depth_buffer_factor;
291 unsigned back_buffer_factor;
292 int i;
293
294 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
295 * enough to add support. Basically, if a context is created with an
296 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
297 * will never be used.
298 */
299 static const GLenum back_buffer_modes[] = {
300 GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
301 };
302
303 uint8_t depth_bits_array[2];
304 uint8_t stencil_bits_array[2];
305 uint8_t msaa_samples_array[1];
306
307 depth_bits_array[0] = depth_bits;
308 depth_bits_array[1] = depth_bits;
309
310 /* Just like with the accumulation buffer, always provide some modes
311 * with a stencil buffer. It will be a sw fallback, but some apps won't
312 * care about that.
313 */
314 stencil_bits_array[0] = stencil_bits;
315 stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
316
317 msaa_samples_array[0] = 0;
318
319 depth_buffer_factor = (stencil_bits == 0) ? 2 : 1;
320 back_buffer_factor = (have_back_buffer) ? 2 : 1;
321
322 if (pixel_bits == 16) {
323 __DRIconfig **configs_a8r8g8b8;
324 __DRIconfig **configs_r5g6b5;
325
326 configs_r5g6b5 = driCreateConfigs(GL_RGB, GL_UNSIGNED_SHORT_5_6_5,
327 depth_bits_array, stencil_bits_array,
328 depth_buffer_factor, back_buffer_modes,
329 back_buffer_factor, msaa_samples_array,
330 1);
331 configs_a8r8g8b8 = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV,
332 depth_bits_array, stencil_bits_array,
333 1, back_buffer_modes, 1,
334 msaa_samples_array, 1);
335 configs = driConcatConfigs(configs_r5g6b5, configs_a8r8g8b8);
336 } else
337 configs = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV,
338 depth_bits_array, stencil_bits_array,
339 depth_buffer_factor,
340 back_buffer_modes, back_buffer_factor,
341 msaa_samples_array, 1);
342
343 if (configs == NULL) {
344 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
345 __func__, __LINE__ );
346 return NULL;
347 }
348
349 /* Mark the visual as slow if there are "fake" stencil bits.
350 */
351 for (i = 0; configs[i]; i++) {
352 m = &configs[i]->modes;
353 if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) {
354 m->visualRating = GLX_SLOW_CONFIG;
355 }
356 }
357
358 return (const __DRIconfig **) configs;
359 }
360
361 #if !RADEON_COMMON
362 static const __DRItexOffsetExtension radeonTexOffsetExtension = {
363 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
364 radeonSetTexOffset,
365 };
366
367 static const __DRItexBufferExtension radeonTexBufferExtension = {
368 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
369 radeonSetTexBuffer,
370 radeonSetTexBuffer2,
371 };
372 #endif
373
374 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
375 static const __DRIallocateExtension r200AllocateExtension = {
376 { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION },
377 r200AllocateMemoryMESA,
378 r200FreeMemoryMESA,
379 r200GetMemoryOffsetMESA
380 };
381
382 static const __DRItexOffsetExtension r200texOffsetExtension = {
383 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
384 r200SetTexOffset,
385 };
386
387 static const __DRItexBufferExtension r200TexBufferExtension = {
388 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
389 r200SetTexBuffer,
390 r200SetTexBuffer2,
391 };
392 #endif
393
394 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
395 static const __DRItexOffsetExtension r300texOffsetExtension = {
396 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
397 r300SetTexOffset,
398 };
399
400 static const __DRItexBufferExtension r300TexBufferExtension = {
401 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
402 r300SetTexBuffer,
403 r300SetTexBuffer2,
404 };
405 #endif
406
407 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
408 static const __DRItexOffsetExtension r600texOffsetExtension = {
409 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
410 r600SetTexOffset, /* +r6/r7 */
411 };
412
413 static const __DRItexBufferExtension r600TexBufferExtension = {
414 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
415 r600SetTexBuffer, /* +r6/r7 */
416 r600SetTexBuffer2, /* +r6/r7 */
417 };
418 #endif
419
420 static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id)
421 {
422 screen->device_id = device_id;
423 screen->chip_flags = 0;
424 switch ( device_id ) {
425 case PCI_CHIP_RADEON_LY:
426 case PCI_CHIP_RADEON_LZ:
427 case PCI_CHIP_RADEON_QY:
428 case PCI_CHIP_RADEON_QZ:
429 case PCI_CHIP_RN50_515E:
430 case PCI_CHIP_RN50_5969:
431 screen->chip_family = CHIP_FAMILY_RV100;
432 break;
433
434 case PCI_CHIP_RS100_4136:
435 case PCI_CHIP_RS100_4336:
436 screen->chip_family = CHIP_FAMILY_RS100;
437 break;
438
439 case PCI_CHIP_RS200_4137:
440 case PCI_CHIP_RS200_4337:
441 case PCI_CHIP_RS250_4237:
442 case PCI_CHIP_RS250_4437:
443 screen->chip_family = CHIP_FAMILY_RS200;
444 break;
445
446 case PCI_CHIP_RADEON_QD:
447 case PCI_CHIP_RADEON_QE:
448 case PCI_CHIP_RADEON_QF:
449 case PCI_CHIP_RADEON_QG:
450 /* all original radeons (7200) presumably have a stencil op bug */
451 screen->chip_family = CHIP_FAMILY_R100;
452 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL;
453 break;
454
455 case PCI_CHIP_RV200_QW:
456 case PCI_CHIP_RV200_QX:
457 case PCI_CHIP_RADEON_LW:
458 case PCI_CHIP_RADEON_LX:
459 screen->chip_family = CHIP_FAMILY_RV200;
460 screen->chip_flags = RADEON_CHIPSET_TCL;
461 break;
462
463 case PCI_CHIP_R200_BB:
464 case PCI_CHIP_R200_BC:
465 case PCI_CHIP_R200_QH:
466 case PCI_CHIP_R200_QL:
467 case PCI_CHIP_R200_QM:
468 screen->chip_family = CHIP_FAMILY_R200;
469 screen->chip_flags = RADEON_CHIPSET_TCL;
470 break;
471
472 case PCI_CHIP_RV250_If:
473 case PCI_CHIP_RV250_Ig:
474 case PCI_CHIP_RV250_Ld:
475 case PCI_CHIP_RV250_Lf:
476 case PCI_CHIP_RV250_Lg:
477 screen->chip_family = CHIP_FAMILY_RV250;
478 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL;
479 break;
480
481 case PCI_CHIP_RV280_5960:
482 case PCI_CHIP_RV280_5961:
483 case PCI_CHIP_RV280_5962:
484 case PCI_CHIP_RV280_5964:
485 case PCI_CHIP_RV280_5965:
486 case PCI_CHIP_RV280_5C61:
487 case PCI_CHIP_RV280_5C63:
488 screen->chip_family = CHIP_FAMILY_RV280;
489 screen->chip_flags = RADEON_CHIPSET_TCL;
490 break;
491
492 case PCI_CHIP_RS300_5834:
493 case PCI_CHIP_RS300_5835:
494 case PCI_CHIP_RS350_7834:
495 case PCI_CHIP_RS350_7835:
496 screen->chip_family = CHIP_FAMILY_RS300;
497 break;
498
499 case PCI_CHIP_R300_AD:
500 case PCI_CHIP_R300_AE:
501 case PCI_CHIP_R300_AF:
502 case PCI_CHIP_R300_AG:
503 case PCI_CHIP_R300_ND:
504 case PCI_CHIP_R300_NE:
505 case PCI_CHIP_R300_NF:
506 case PCI_CHIP_R300_NG:
507 screen->chip_family = CHIP_FAMILY_R300;
508 screen->chip_flags = RADEON_CHIPSET_TCL;
509 break;
510
511 case PCI_CHIP_RV350_AP:
512 case PCI_CHIP_RV350_AQ:
513 case PCI_CHIP_RV350_AR:
514 case PCI_CHIP_RV350_AS:
515 case PCI_CHIP_RV350_AT:
516 case PCI_CHIP_RV350_AV:
517 case PCI_CHIP_RV350_AU:
518 case PCI_CHIP_RV350_NP:
519 case PCI_CHIP_RV350_NQ:
520 case PCI_CHIP_RV350_NR:
521 case PCI_CHIP_RV350_NS:
522 case PCI_CHIP_RV350_NT:
523 case PCI_CHIP_RV350_NV:
524 screen->chip_family = CHIP_FAMILY_RV350;
525 screen->chip_flags = RADEON_CHIPSET_TCL;
526 break;
527
528 case PCI_CHIP_R350_AH:
529 case PCI_CHIP_R350_AI:
530 case PCI_CHIP_R350_AJ:
531 case PCI_CHIP_R350_AK:
532 case PCI_CHIP_R350_NH:
533 case PCI_CHIP_R350_NI:
534 case PCI_CHIP_R360_NJ:
535 case PCI_CHIP_R350_NK:
536 screen->chip_family = CHIP_FAMILY_R350;
537 screen->chip_flags = RADEON_CHIPSET_TCL;
538 break;
539
540 case PCI_CHIP_RV370_5460:
541 case PCI_CHIP_RV370_5462:
542 case PCI_CHIP_RV370_5464:
543 case PCI_CHIP_RV370_5B60:
544 case PCI_CHIP_RV370_5B62:
545 case PCI_CHIP_RV370_5B63:
546 case PCI_CHIP_RV370_5B64:
547 case PCI_CHIP_RV370_5B65:
548 case PCI_CHIP_RV380_3150:
549 case PCI_CHIP_RV380_3152:
550 case PCI_CHIP_RV380_3154:
551 case PCI_CHIP_RV380_3E50:
552 case PCI_CHIP_RV380_3E54:
553 screen->chip_family = CHIP_FAMILY_RV380;
554 screen->chip_flags = RADEON_CHIPSET_TCL;
555 break;
556
557 case PCI_CHIP_R420_JN:
558 case PCI_CHIP_R420_JH:
559 case PCI_CHIP_R420_JI:
560 case PCI_CHIP_R420_JJ:
561 case PCI_CHIP_R420_JK:
562 case PCI_CHIP_R420_JL:
563 case PCI_CHIP_R420_JM:
564 case PCI_CHIP_R420_JO:
565 case PCI_CHIP_R420_JP:
566 case PCI_CHIP_R420_JT:
567 case PCI_CHIP_R481_4B49:
568 case PCI_CHIP_R481_4B4A:
569 case PCI_CHIP_R481_4B4B:
570 case PCI_CHIP_R481_4B4C:
571 case PCI_CHIP_R423_UH:
572 case PCI_CHIP_R423_UI:
573 case PCI_CHIP_R423_UJ:
574 case PCI_CHIP_R423_UK:
575 case PCI_CHIP_R430_554C:
576 case PCI_CHIP_R430_554D:
577 case PCI_CHIP_R430_554E:
578 case PCI_CHIP_R430_554F:
579 case PCI_CHIP_R423_5550:
580 case PCI_CHIP_R423_UQ:
581 case PCI_CHIP_R423_UR:
582 case PCI_CHIP_R423_UT:
583 case PCI_CHIP_R430_5D48:
584 case PCI_CHIP_R430_5D49:
585 case PCI_CHIP_R430_5D4A:
586 case PCI_CHIP_R480_5D4C:
587 case PCI_CHIP_R480_5D4D:
588 case PCI_CHIP_R480_5D4E:
589 case PCI_CHIP_R480_5D4F:
590 case PCI_CHIP_R480_5D50:
591 case PCI_CHIP_R480_5D52:
592 case PCI_CHIP_R423_5D57:
593 screen->chip_family = CHIP_FAMILY_R420;
594 screen->chip_flags = RADEON_CHIPSET_TCL;
595 break;
596
597 case PCI_CHIP_RV410_5E4C:
598 case PCI_CHIP_RV410_5E4F:
599 case PCI_CHIP_RV410_564A:
600 case PCI_CHIP_RV410_564B:
601 case PCI_CHIP_RV410_564F:
602 case PCI_CHIP_RV410_5652:
603 case PCI_CHIP_RV410_5653:
604 case PCI_CHIP_RV410_5657:
605 case PCI_CHIP_RV410_5E48:
606 case PCI_CHIP_RV410_5E4A:
607 case PCI_CHIP_RV410_5E4B:
608 case PCI_CHIP_RV410_5E4D:
609 screen->chip_family = CHIP_FAMILY_RV410;
610 screen->chip_flags = RADEON_CHIPSET_TCL;
611 break;
612
613 case PCI_CHIP_RS480_5954:
614 case PCI_CHIP_RS480_5955:
615 case PCI_CHIP_RS482_5974:
616 case PCI_CHIP_RS482_5975:
617 case PCI_CHIP_RS400_5A41:
618 case PCI_CHIP_RS400_5A42:
619 case PCI_CHIP_RC410_5A61:
620 case PCI_CHIP_RC410_5A62:
621 screen->chip_family = CHIP_FAMILY_RS400;
622 break;
623
624 case PCI_CHIP_RS600_793F:
625 case PCI_CHIP_RS600_7941:
626 case PCI_CHIP_RS600_7942:
627 screen->chip_family = CHIP_FAMILY_RS600;
628 break;
629
630 case PCI_CHIP_RS690_791E:
631 case PCI_CHIP_RS690_791F:
632 screen->chip_family = CHIP_FAMILY_RS690;
633 break;
634 case PCI_CHIP_RS740_796C:
635 case PCI_CHIP_RS740_796D:
636 case PCI_CHIP_RS740_796E:
637 case PCI_CHIP_RS740_796F:
638 screen->chip_family = CHIP_FAMILY_RS740;
639 break;
640
641 case PCI_CHIP_R520_7100:
642 case PCI_CHIP_R520_7101:
643 case PCI_CHIP_R520_7102:
644 case PCI_CHIP_R520_7103:
645 case PCI_CHIP_R520_7104:
646 case PCI_CHIP_R520_7105:
647 case PCI_CHIP_R520_7106:
648 case PCI_CHIP_R520_7108:
649 case PCI_CHIP_R520_7109:
650 case PCI_CHIP_R520_710A:
651 case PCI_CHIP_R520_710B:
652 case PCI_CHIP_R520_710C:
653 case PCI_CHIP_R520_710E:
654 case PCI_CHIP_R520_710F:
655 screen->chip_family = CHIP_FAMILY_R520;
656 screen->chip_flags = RADEON_CHIPSET_TCL;
657 break;
658
659 case PCI_CHIP_RV515_7140:
660 case PCI_CHIP_RV515_7141:
661 case PCI_CHIP_RV515_7142:
662 case PCI_CHIP_RV515_7143:
663 case PCI_CHIP_RV515_7144:
664 case PCI_CHIP_RV515_7145:
665 case PCI_CHIP_RV515_7146:
666 case PCI_CHIP_RV515_7147:
667 case PCI_CHIP_RV515_7149:
668 case PCI_CHIP_RV515_714A:
669 case PCI_CHIP_RV515_714B:
670 case PCI_CHIP_RV515_714C:
671 case PCI_CHIP_RV515_714D:
672 case PCI_CHIP_RV515_714E:
673 case PCI_CHIP_RV515_714F:
674 case PCI_CHIP_RV515_7151:
675 case PCI_CHIP_RV515_7152:
676 case PCI_CHIP_RV515_7153:
677 case PCI_CHIP_RV515_715E:
678 case PCI_CHIP_RV515_715F:
679 case PCI_CHIP_RV515_7180:
680 case PCI_CHIP_RV515_7181:
681 case PCI_CHIP_RV515_7183:
682 case PCI_CHIP_RV515_7186:
683 case PCI_CHIP_RV515_7187:
684 case PCI_CHIP_RV515_7188:
685 case PCI_CHIP_RV515_718A:
686 case PCI_CHIP_RV515_718B:
687 case PCI_CHIP_RV515_718C:
688 case PCI_CHIP_RV515_718D:
689 case PCI_CHIP_RV515_718F:
690 case PCI_CHIP_RV515_7193:
691 case PCI_CHIP_RV515_7196:
692 case PCI_CHIP_RV515_719B:
693 case PCI_CHIP_RV515_719F:
694 case PCI_CHIP_RV515_7200:
695 case PCI_CHIP_RV515_7210:
696 case PCI_CHIP_RV515_7211:
697 screen->chip_family = CHIP_FAMILY_RV515;
698 screen->chip_flags = RADEON_CHIPSET_TCL;
699 break;
700
701 case PCI_CHIP_RV530_71C0:
702 case PCI_CHIP_RV530_71C1:
703 case PCI_CHIP_RV530_71C2:
704 case PCI_CHIP_RV530_71C3:
705 case PCI_CHIP_RV530_71C4:
706 case PCI_CHIP_RV530_71C5:
707 case PCI_CHIP_RV530_71C6:
708 case PCI_CHIP_RV530_71C7:
709 case PCI_CHIP_RV530_71CD:
710 case PCI_CHIP_RV530_71CE:
711 case PCI_CHIP_RV530_71D2:
712 case PCI_CHIP_RV530_71D4:
713 case PCI_CHIP_RV530_71D5:
714 case PCI_CHIP_RV530_71D6:
715 case PCI_CHIP_RV530_71DA:
716 case PCI_CHIP_RV530_71DE:
717 screen->chip_family = CHIP_FAMILY_RV530;
718 screen->chip_flags = RADEON_CHIPSET_TCL;
719 break;
720
721 case PCI_CHIP_R580_7240:
722 case PCI_CHIP_R580_7243:
723 case PCI_CHIP_R580_7244:
724 case PCI_CHIP_R580_7245:
725 case PCI_CHIP_R580_7246:
726 case PCI_CHIP_R580_7247:
727 case PCI_CHIP_R580_7248:
728 case PCI_CHIP_R580_7249:
729 case PCI_CHIP_R580_724A:
730 case PCI_CHIP_R580_724B:
731 case PCI_CHIP_R580_724C:
732 case PCI_CHIP_R580_724D:
733 case PCI_CHIP_R580_724E:
734 case PCI_CHIP_R580_724F:
735 case PCI_CHIP_R580_7284:
736 screen->chip_family = CHIP_FAMILY_R580;
737 screen->chip_flags = RADEON_CHIPSET_TCL;
738 break;
739
740 case PCI_CHIP_RV570_7280:
741 case PCI_CHIP_RV560_7281:
742 case PCI_CHIP_RV560_7283:
743 case PCI_CHIP_RV560_7287:
744 case PCI_CHIP_RV570_7288:
745 case PCI_CHIP_RV570_7289:
746 case PCI_CHIP_RV570_728B:
747 case PCI_CHIP_RV570_728C:
748 case PCI_CHIP_RV560_7290:
749 case PCI_CHIP_RV560_7291:
750 case PCI_CHIP_RV560_7293:
751 case PCI_CHIP_RV560_7297:
752 screen->chip_family = CHIP_FAMILY_RV560;
753 screen->chip_flags = RADEON_CHIPSET_TCL;
754 break;
755
756 case PCI_CHIP_R600_9400:
757 case PCI_CHIP_R600_9401:
758 case PCI_CHIP_R600_9402:
759 case PCI_CHIP_R600_9403:
760 case PCI_CHIP_R600_9405:
761 case PCI_CHIP_R600_940A:
762 case PCI_CHIP_R600_940B:
763 case PCI_CHIP_R600_940F:
764 screen->chip_family = CHIP_FAMILY_R600;
765 screen->chip_flags = RADEON_CHIPSET_TCL;
766 break;
767
768 case PCI_CHIP_RV610_94C0:
769 case PCI_CHIP_RV610_94C1:
770 case PCI_CHIP_RV610_94C3:
771 case PCI_CHIP_RV610_94C4:
772 case PCI_CHIP_RV610_94C5:
773 case PCI_CHIP_RV610_94C6:
774 case PCI_CHIP_RV610_94C7:
775 case PCI_CHIP_RV610_94C8:
776 case PCI_CHIP_RV610_94C9:
777 case PCI_CHIP_RV610_94CB:
778 case PCI_CHIP_RV610_94CC:
779 case PCI_CHIP_RV610_94CD:
780 screen->chip_family = CHIP_FAMILY_RV610;
781 screen->chip_flags = RADEON_CHIPSET_TCL;
782 break;
783
784 case PCI_CHIP_RV630_9580:
785 case PCI_CHIP_RV630_9581:
786 case PCI_CHIP_RV630_9583:
787 case PCI_CHIP_RV630_9586:
788 case PCI_CHIP_RV630_9587:
789 case PCI_CHIP_RV630_9588:
790 case PCI_CHIP_RV630_9589:
791 case PCI_CHIP_RV630_958A:
792 case PCI_CHIP_RV630_958B:
793 case PCI_CHIP_RV630_958C:
794 case PCI_CHIP_RV630_958D:
795 case PCI_CHIP_RV630_958E:
796 case PCI_CHIP_RV630_958F:
797 screen->chip_family = CHIP_FAMILY_RV630;
798 screen->chip_flags = RADEON_CHIPSET_TCL;
799 break;
800
801 case PCI_CHIP_RV670_9500:
802 case PCI_CHIP_RV670_9501:
803 case PCI_CHIP_RV670_9504:
804 case PCI_CHIP_RV670_9505:
805 case PCI_CHIP_RV670_9506:
806 case PCI_CHIP_RV670_9507:
807 case PCI_CHIP_RV670_9508:
808 case PCI_CHIP_RV670_9509:
809 case PCI_CHIP_RV670_950F:
810 case PCI_CHIP_RV670_9511:
811 case PCI_CHIP_RV670_9515:
812 case PCI_CHIP_RV670_9517:
813 case PCI_CHIP_RV670_9519:
814 screen->chip_family = CHIP_FAMILY_RV670;
815 screen->chip_flags = RADEON_CHIPSET_TCL;
816 break;
817
818 case PCI_CHIP_RV620_95C0:
819 case PCI_CHIP_RV620_95C2:
820 case PCI_CHIP_RV620_95C4:
821 case PCI_CHIP_RV620_95C5:
822 case PCI_CHIP_RV620_95C6:
823 case PCI_CHIP_RV620_95C7:
824 case PCI_CHIP_RV620_95C9:
825 case PCI_CHIP_RV620_95CC:
826 case PCI_CHIP_RV620_95CD:
827 case PCI_CHIP_RV620_95CE:
828 case PCI_CHIP_RV620_95CF:
829 screen->chip_family = CHIP_FAMILY_RV620;
830 screen->chip_flags = RADEON_CHIPSET_TCL;
831 break;
832
833 case PCI_CHIP_RV635_9590:
834 case PCI_CHIP_RV635_9591:
835 case PCI_CHIP_RV635_9593:
836 case PCI_CHIP_RV635_9595:
837 case PCI_CHIP_RV635_9596:
838 case PCI_CHIP_RV635_9597:
839 case PCI_CHIP_RV635_9598:
840 case PCI_CHIP_RV635_9599:
841 case PCI_CHIP_RV635_959B:
842 screen->chip_family = CHIP_FAMILY_RV635;
843 screen->chip_flags = RADEON_CHIPSET_TCL;
844 break;
845
846 case PCI_CHIP_RS780_9610:
847 case PCI_CHIP_RS780_9611:
848 case PCI_CHIP_RS780_9612:
849 case PCI_CHIP_RS780_9613:
850 case PCI_CHIP_RS780_9614:
851 case PCI_CHIP_RS780_9615:
852 case PCI_CHIP_RS780_9616:
853 screen->chip_family = CHIP_FAMILY_RS780;
854 screen->chip_flags = RADEON_CHIPSET_TCL;
855 break;
856
857 case PCI_CHIP_RV770_9440:
858 case PCI_CHIP_RV770_9441:
859 case PCI_CHIP_RV770_9442:
860 case PCI_CHIP_RV770_9444:
861 case PCI_CHIP_RV770_9446:
862 case PCI_CHIP_RV770_944A:
863 case PCI_CHIP_RV770_944B:
864 case PCI_CHIP_RV770_944C:
865 case PCI_CHIP_RV770_944E:
866 case PCI_CHIP_RV770_9450:
867 case PCI_CHIP_RV770_9452:
868 case PCI_CHIP_RV770_9456:
869 case PCI_CHIP_RV770_945A:
870 case PCI_CHIP_RV770_945B:
871 case PCI_CHIP_RV790_9460:
872 case PCI_CHIP_RV790_9462:
873 case PCI_CHIP_RV770_946A:
874 case PCI_CHIP_RV770_946B:
875 case PCI_CHIP_RV770_947A:
876 case PCI_CHIP_RV770_947B:
877 screen->chip_family = CHIP_FAMILY_RV770;
878 screen->chip_flags = RADEON_CHIPSET_TCL;
879 break;
880
881 case PCI_CHIP_RV730_9480:
882 case PCI_CHIP_RV730_9487:
883 case PCI_CHIP_RV730_9488:
884 case PCI_CHIP_RV730_9489:
885 case PCI_CHIP_RV730_948F:
886 case PCI_CHIP_RV730_9490:
887 case PCI_CHIP_RV730_9491:
888 case PCI_CHIP_RV730_9495:
889 case PCI_CHIP_RV730_9498:
890 case PCI_CHIP_RV730_949C:
891 case PCI_CHIP_RV730_949E:
892 case PCI_CHIP_RV730_949F:
893 screen->chip_family = CHIP_FAMILY_RV730;
894 screen->chip_flags = RADEON_CHIPSET_TCL;
895 break;
896
897 case PCI_CHIP_RV710_9540:
898 case PCI_CHIP_RV710_9541:
899 case PCI_CHIP_RV710_9542:
900 case PCI_CHIP_RV710_954E:
901 case PCI_CHIP_RV710_954F:
902 case PCI_CHIP_RV710_9552:
903 case PCI_CHIP_RV710_9553:
904 case PCI_CHIP_RV710_9555:
905 case PCI_CHIP_RV710_9557:
906 screen->chip_family = CHIP_FAMILY_RV710;
907 screen->chip_flags = RADEON_CHIPSET_TCL;
908 break;
909
910 case PCI_CHIP_RV740_94A0:
911 case PCI_CHIP_RV740_94A1:
912 case PCI_CHIP_RV740_94A3:
913 case PCI_CHIP_RV740_94B1:
914 case PCI_CHIP_RV740_94B3:
915 case PCI_CHIP_RV740_94B4:
916 case PCI_CHIP_RV740_94B5:
917 case PCI_CHIP_RV740_94B9:
918 screen->chip_family = CHIP_FAMILY_RV740;
919 screen->chip_flags = RADEON_CHIPSET_TCL;
920 break;
921
922 default:
923 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
924 device_id);
925 return -1;
926 }
927
928 return 0;
929 }
930
931
932 /* Create the device specific screen private data struct.
933 */
934 static radeonScreenPtr
935 radeonCreateScreen( __DRIscreenPrivate *sPriv )
936 {
937 radeonScreenPtr screen;
938 RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
939 unsigned char *RADEONMMIO = NULL;
940 int i;
941 int ret;
942 uint32_t temp = 0;
943
944 if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) {
945 fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n");
946 return GL_FALSE;
947 }
948
949 /* Allocate the private area */
950 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
951 if ( !screen ) {
952 __driUtilMessage("%s: Could not allocate memory for screen structure",
953 __FUNCTION__);
954 return NULL;
955 }
956
957 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
958 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
959 #endif
960 /* parse information in __driConfigOptions */
961 driParseOptionInfo (&screen->optionCache,
962 __driConfigOptions, __driNConfigOptions);
963
964 /* This is first since which regions we map depends on whether or
965 * not we are using a PCI card.
966 */
967 screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP);
968 {
969 int ret;
970
971 ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BUFFER_OFFSET,
972 &screen->gart_buffer_offset);
973
974 if (ret) {
975 FREE( screen );
976 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
977 return NULL;
978 }
979
980 ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BASE,
981 &screen->gart_base);
982 if (ret) {
983 FREE( screen );
984 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret);
985 return NULL;
986 }
987
988 ret = radeonGetParam(sPriv, RADEON_PARAM_IRQ_NR,
989 &screen->irq);
990 if (ret) {
991 FREE( screen );
992 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
993 return NULL;
994 }
995 screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7);
996 screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11);
997 screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16);
998 screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18);
999 screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13);
1000 screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15);
1001 screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25);
1002 screen->drmSupportsOcclusionQueries = (sPriv->drm_version.minor >= 30);
1003 }
1004
1005 ret = radeon_set_screen_flags(screen, dri_priv->deviceID);
1006 if (ret == -1)
1007 return NULL;
1008
1009 screen->mmio.handle = dri_priv->registerHandle;
1010 screen->mmio.size = dri_priv->registerSize;
1011 if ( drmMap( sPriv->fd,
1012 screen->mmio.handle,
1013 screen->mmio.size,
1014 &screen->mmio.map ) ) {
1015 FREE( screen );
1016 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
1017 return NULL;
1018 }
1019
1020 RADEONMMIO = screen->mmio.map;
1021
1022 screen->status.handle = dri_priv->statusHandle;
1023 screen->status.size = dri_priv->statusSize;
1024 if ( drmMap( sPriv->fd,
1025 screen->status.handle,
1026 screen->status.size,
1027 &screen->status.map ) ) {
1028 drmUnmap( screen->mmio.map, screen->mmio.size );
1029 FREE( screen );
1030 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
1031 return NULL;
1032 }
1033 if (screen->chip_family < CHIP_FAMILY_R600)
1034 screen->scratch = (__volatile__ uint32_t *)
1035 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
1036 else
1037 screen->scratch = (__volatile__ uint32_t *)
1038 ((GLubyte *)screen->status.map + R600_SCRATCH_REG_OFFSET);
1039
1040 screen->buffers = drmMapBufs( sPriv->fd );
1041 if ( !screen->buffers ) {
1042 drmUnmap( screen->status.map, screen->status.size );
1043 drmUnmap( screen->mmio.map, screen->mmio.size );
1044 FREE( screen );
1045 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
1046 return NULL;
1047 }
1048
1049 if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
1050 screen->gartTextures.handle = dri_priv->gartTexHandle;
1051 screen->gartTextures.size = dri_priv->gartTexMapSize;
1052 if ( drmMap( sPriv->fd,
1053 screen->gartTextures.handle,
1054 screen->gartTextures.size,
1055 (drmAddressPtr)&screen->gartTextures.map ) ) {
1056 drmUnmapBufs( screen->buffers );
1057 drmUnmap( screen->status.map, screen->status.size );
1058 drmUnmap( screen->mmio.map, screen->mmio.size );
1059 FREE( screen );
1060 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
1061 return NULL;
1062 }
1063
1064 screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base;
1065 }
1066
1067 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) &&
1068 sPriv->ddx_version.minor < 2) {
1069 fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
1070 return NULL;
1071 }
1072
1073 if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) {
1074 fprintf(stderr, "R500 support requires a newer drm.\n");
1075 return NULL;
1076 }
1077
1078 if (getenv("R300_NO_TCL"))
1079 screen->chip_flags &= ~RADEON_CHIPSET_TCL;
1080
1081 if (screen->chip_family <= CHIP_FAMILY_RS200)
1082 screen->chip_flags |= RADEON_CLASS_R100;
1083 else if (screen->chip_family <= CHIP_FAMILY_RV280)
1084 screen->chip_flags |= RADEON_CLASS_R200;
1085 else if (screen->chip_family <= CHIP_FAMILY_RV570)
1086 screen->chip_flags |= RADEON_CLASS_R300;
1087 else
1088 screen->chip_flags |= RADEON_CLASS_R600;
1089
1090 screen->cpp = dri_priv->bpp / 8;
1091 screen->AGPMode = dri_priv->AGPMode;
1092
1093 ret = radeonGetParam(sPriv, RADEON_PARAM_FB_LOCATION, &temp);
1094
1095 /* +r6/r7 */
1096 if(screen->chip_family >= CHIP_FAMILY_R600)
1097 {
1098 if (ret)
1099 {
1100 FREE( screen );
1101 fprintf(stderr, "Unable to get fb location need newer drm\n");
1102 return NULL;
1103 }
1104 else
1105 {
1106 screen->fbLocation = (temp & 0xffff) << 24;
1107 }
1108 }
1109 else
1110 {
1111 if (ret)
1112 {
1113 if (screen->chip_family < CHIP_FAMILY_RS600 && !screen->kernel_mm)
1114 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16;
1115 else
1116 {
1117 FREE( screen );
1118 fprintf(stderr, "Unable to get fb location need newer drm\n");
1119 return NULL;
1120 }
1121 }
1122 else
1123 {
1124 screen->fbLocation = (temp & 0xffff) << 16;
1125 }
1126 }
1127
1128 if (IS_R300_CLASS(screen)) {
1129 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp);
1130 if (ret) {
1131 fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
1132 switch (screen->chip_family) {
1133 case CHIP_FAMILY_R300:
1134 case CHIP_FAMILY_R350:
1135 screen->num_gb_pipes = 2;
1136 break;
1137 case CHIP_FAMILY_R420:
1138 case CHIP_FAMILY_R520:
1139 case CHIP_FAMILY_R580:
1140 case CHIP_FAMILY_RV560:
1141 case CHIP_FAMILY_RV570:
1142 screen->num_gb_pipes = 4;
1143 break;
1144 case CHIP_FAMILY_RV350:
1145 case CHIP_FAMILY_RV515:
1146 case CHIP_FAMILY_RV530:
1147 case CHIP_FAMILY_RV410:
1148 default:
1149 screen->num_gb_pipes = 1;
1150 break;
1151 }
1152 } else {
1153 screen->num_gb_pipes = temp;
1154 }
1155
1156 /* pipe overrides */
1157 switch (dri_priv->deviceID) {
1158 case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
1159 case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */
1160 case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */
1161 screen->num_gb_pipes = 1;
1162 break;
1163 default:
1164 break;
1165 }
1166 }
1167
1168 if ( sPriv->drm_version.minor >= 10 ) {
1169 drm_radeon_setparam_t sp;
1170
1171 sp.param = RADEON_SETPARAM_FB_LOCATION;
1172 sp.value = screen->fbLocation;
1173
1174 drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
1175 &sp, sizeof( sp ) );
1176 }
1177
1178 screen->frontOffset = dri_priv->frontOffset;
1179 screen->frontPitch = dri_priv->frontPitch;
1180 screen->backOffset = dri_priv->backOffset;
1181 screen->backPitch = dri_priv->backPitch;
1182 screen->depthOffset = dri_priv->depthOffset;
1183 screen->depthPitch = dri_priv->depthPitch;
1184
1185 /* Check if ddx has set up a surface reg to cover depth buffer */
1186 screen->depthHasSurface = (sPriv->ddx_version.major > 4) ||
1187 /* these chips don't use tiled z without hyperz. So always pretend
1188 we have set up a surface which will cause linear reads/writes */
1189 (IS_R100_CLASS(screen) &&
1190 !(screen->chip_flags & RADEON_CHIPSET_TCL));
1191
1192 if ( dri_priv->textureSize == 0 ) {
1193 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset;
1194 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize;
1195 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
1196 dri_priv->log2GARTTexGran;
1197 } else {
1198 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
1199 + screen->fbLocation;
1200 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
1201 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
1202 dri_priv->log2TexGran;
1203 }
1204
1205 if ( !screen->gartTextures.map || dri_priv->textureSize == 0
1206 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
1207 screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
1208 screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
1209 screen->texSize[RADEON_GART_TEX_HEAP] = 0;
1210 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
1211 } else {
1212 screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
1213 screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
1214 screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
1215 screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
1216 dri_priv->log2GARTTexGran;
1217 }
1218
1219 i = 0;
1220 screen->extensions[i++] = &driCopySubBufferExtension.base;
1221 screen->extensions[i++] = &driFrameTrackingExtension.base;
1222 screen->extensions[i++] = &driReadDrawableExtension;
1223
1224 if ( screen->irq != 0 ) {
1225 screen->extensions[i++] = &driSwapControlExtension.base;
1226 screen->extensions[i++] = &driMediaStreamCounterExtension.base;
1227 }
1228
1229 #if !RADEON_COMMON
1230 screen->extensions[i++] = &radeonTexOffsetExtension.base;
1231 #endif
1232
1233 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1234 if (IS_R200_CLASS(screen))
1235 screen->extensions[i++] = &r200AllocateExtension.base;
1236
1237 screen->extensions[i++] = &r200texOffsetExtension.base;
1238 #endif
1239
1240 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1241 screen->extensions[i++] = &r300texOffsetExtension.base;
1242 #endif
1243
1244 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
1245 screen->extensions[i++] = &r600texOffsetExtension.base;
1246 #endif
1247
1248 screen->extensions[i++] = NULL;
1249 sPriv->extensions = screen->extensions;
1250
1251 screen->driScreen = sPriv;
1252 screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
1253 screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA +
1254 screen->sarea_priv_offset);
1255
1256 screen->bom = radeon_bo_manager_legacy_ctor(screen);
1257 if (screen->bom == NULL) {
1258 free(screen);
1259 return NULL;
1260 }
1261
1262 return screen;
1263 }
1264
1265 static radeonScreenPtr
1266 radeonCreateScreen2(__DRIscreenPrivate *sPriv)
1267 {
1268 radeonScreenPtr screen;
1269 int i;
1270 int ret;
1271 uint32_t device_id = 0;
1272 uint32_t temp = 0;
1273
1274 /* Allocate the private area */
1275 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
1276 if ( !screen ) {
1277 __driUtilMessage("%s: Could not allocate memory for screen structure",
1278 __FUNCTION__);
1279 fprintf(stderr, "leaving here\n");
1280 return NULL;
1281 }
1282
1283 #if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1284 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
1285 #endif
1286
1287 /* parse information in __driConfigOptions */
1288 driParseOptionInfo (&screen->optionCache,
1289 __driConfigOptions, __driNConfigOptions);
1290
1291 screen->kernel_mm = 1;
1292 screen->chip_flags = 0;
1293
1294 /* if we have kms we can support all of these */
1295 screen->drmSupportsCubeMapsR200 = 1;
1296 screen->drmSupportsBlendColor = 1;
1297 screen->drmSupportsTriPerf = 1;
1298 screen->drmSupportsFragShader = 1;
1299 screen->drmSupportsPointSprites = 1;
1300 screen->drmSupportsCubeMapsR100 = 1;
1301 screen->drmSupportsVertexProgram = 1;
1302 screen->drmSupportsOcclusionQueries = 1;
1303 screen->irq = 1;
1304
1305 ret = radeonGetParam(sPriv, RADEON_PARAM_DEVICE_ID, &device_id);
1306 if (ret) {
1307 FREE( screen );
1308 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret);
1309 return NULL;
1310 }
1311
1312 ret = radeon_set_screen_flags(screen, device_id);
1313 if (ret == -1)
1314 return NULL;
1315
1316 if (getenv("R300_NO_TCL"))
1317 screen->chip_flags &= ~RADEON_CHIPSET_TCL;
1318
1319 if (screen->chip_family <= CHIP_FAMILY_RS200)
1320 screen->chip_flags |= RADEON_CLASS_R100;
1321 else if (screen->chip_family <= CHIP_FAMILY_RV280)
1322 screen->chip_flags |= RADEON_CLASS_R200;
1323 else if (screen->chip_family <= CHIP_FAMILY_RV570)
1324 screen->chip_flags |= RADEON_CLASS_R300;
1325 else
1326 screen->chip_flags |= RADEON_CLASS_R600;
1327
1328 if (IS_R300_CLASS(screen)) {
1329 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp);
1330 if (ret) {
1331 fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
1332 switch (screen->chip_family) {
1333 case CHIP_FAMILY_R300:
1334 case CHIP_FAMILY_R350:
1335 screen->num_gb_pipes = 2;
1336 break;
1337 case CHIP_FAMILY_R420:
1338 case CHIP_FAMILY_R520:
1339 case CHIP_FAMILY_R580:
1340 case CHIP_FAMILY_RV560:
1341 case CHIP_FAMILY_RV570:
1342 screen->num_gb_pipes = 4;
1343 break;
1344 case CHIP_FAMILY_RV350:
1345 case CHIP_FAMILY_RV515:
1346 case CHIP_FAMILY_RV530:
1347 case CHIP_FAMILY_RV410:
1348 default:
1349 screen->num_gb_pipes = 1;
1350 break;
1351 }
1352 } else {
1353 screen->num_gb_pipes = temp;
1354 }
1355
1356 /* pipe overrides */
1357 switch (device_id) {
1358 case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
1359 case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */
1360 case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */
1361 screen->num_gb_pipes = 1;
1362 break;
1363 default:
1364 break;
1365 }
1366
1367 }
1368
1369 i = 0;
1370 screen->extensions[i++] = &driCopySubBufferExtension.base;
1371 screen->extensions[i++] = &driFrameTrackingExtension.base;
1372 screen->extensions[i++] = &driReadDrawableExtension;
1373
1374 if ( screen->irq != 0 ) {
1375 screen->extensions[i++] = &driSwapControlExtension.base;
1376 screen->extensions[i++] = &driMediaStreamCounterExtension.base;
1377 }
1378
1379 #if !RADEON_COMMON
1380 screen->extensions[i++] = &radeonTexBufferExtension.base;
1381 #endif
1382
1383 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1384 if (IS_R200_CLASS(screen))
1385 screen->extensions[i++] = &r200AllocateExtension.base;
1386
1387 screen->extensions[i++] = &r200TexBufferExtension.base;
1388 #endif
1389
1390 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1391 screen->extensions[i++] = &r300TexBufferExtension.base;
1392 #endif
1393
1394 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
1395 screen->extensions[i++] = &r600TexBufferExtension.base;
1396 #endif
1397
1398 screen->extensions[i++] = NULL;
1399 sPriv->extensions = screen->extensions;
1400
1401 screen->driScreen = sPriv;
1402 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd);
1403 if (screen->bom == NULL) {
1404 free(screen);
1405 return NULL;
1406 }
1407 return screen;
1408 }
1409
1410 /* Destroy the device specific screen private data struct.
1411 */
1412 static void
1413 radeonDestroyScreen( __DRIscreenPrivate *sPriv )
1414 {
1415 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
1416
1417 if (!screen)
1418 return;
1419
1420 if (screen->kernel_mm) {
1421 #ifdef RADEON_BO_TRACK
1422 radeon_tracker_print(&screen->bom->tracker, stderr);
1423 #endif
1424 radeon_bo_manager_gem_dtor(screen->bom);
1425 } else {
1426 radeon_bo_manager_legacy_dtor(screen->bom);
1427
1428 if ( screen->gartTextures.map ) {
1429 drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
1430 }
1431 drmUnmapBufs( screen->buffers );
1432 drmUnmap( screen->status.map, screen->status.size );
1433 drmUnmap( screen->mmio.map, screen->mmio.size );
1434 }
1435
1436 /* free all option information */
1437 driDestroyOptionInfo (&screen->optionCache);
1438
1439 FREE( screen );
1440 sPriv->private = NULL;
1441 }
1442
1443
1444 /* Initialize the driver specific screen private data.
1445 */
1446 static GLboolean
1447 radeonInitDriver( __DRIscreenPrivate *sPriv )
1448 {
1449 if (sPriv->dri2.enabled) {
1450 sPriv->private = (void *) radeonCreateScreen2( sPriv );
1451 } else {
1452 sPriv->private = (void *) radeonCreateScreen( sPriv );
1453 }
1454 if ( !sPriv->private ) {
1455 radeonDestroyScreen( sPriv );
1456 return GL_FALSE;
1457 }
1458
1459 return GL_TRUE;
1460 }
1461
1462
1463
1464 /**
1465 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
1466 *
1467 * \todo This function (and its interface) will need to be updated to support
1468 * pbuffers.
1469 */
1470 static GLboolean
1471 radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
1472 __DRIdrawablePrivate *driDrawPriv,
1473 const __GLcontextModes *mesaVis,
1474 GLboolean isPixmap )
1475 {
1476 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
1477
1478 const GLboolean swDepth = GL_FALSE;
1479 const GLboolean swAlpha = GL_FALSE;
1480 const GLboolean swAccum = mesaVis->accumRedBits > 0;
1481 const GLboolean swStencil = mesaVis->stencilBits > 0 &&
1482 mesaVis->depthBits != 24;
1483 GLenum rgbFormat;
1484 struct radeon_framebuffer *rfb;
1485
1486 if (isPixmap)
1487 return GL_FALSE; /* not implemented */
1488
1489 rfb = CALLOC_STRUCT(radeon_framebuffer);
1490 if (!rfb)
1491 return GL_FALSE;
1492
1493 _mesa_initialize_framebuffer(&rfb->base, mesaVis);
1494
1495 if (mesaVis->redBits == 5)
1496 rgbFormat = GL_RGB5;
1497 else if (mesaVis->alphaBits == 0)
1498 rgbFormat = GL_RGB8;
1499 else
1500 rgbFormat = GL_RGBA8;
1501
1502 /* front color renderbuffer */
1503 rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1504 _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base);
1505 rfb->color_rb[0]->has_surface = 1;
1506
1507 /* back color renderbuffer */
1508 if (mesaVis->doubleBufferMode) {
1509 rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1510 _mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base);
1511 rfb->color_rb[1]->has_surface = 1;
1512 }
1513
1514 if (mesaVis->depthBits == 24) {
1515 if (mesaVis->stencilBits == 8) {
1516 struct radeon_renderbuffer *depthStencilRb = radeon_create_renderbuffer(GL_DEPTH24_STENCIL8_EXT, driDrawPriv);
1517 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base);
1518 _mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &depthStencilRb->base);
1519 depthStencilRb->has_surface = screen->depthHasSurface;
1520 } else {
1521 /* depth renderbuffer */
1522 struct radeon_renderbuffer *depth = radeon_create_renderbuffer(GL_DEPTH_COMPONENT24, driDrawPriv);
1523 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base);
1524 depth->has_surface = screen->depthHasSurface;
1525 }
1526 } else if (mesaVis->depthBits == 16) {
1527 /* just 16-bit depth buffer, no hw stencil */
1528 struct radeon_renderbuffer *depth = radeon_create_renderbuffer(GL_DEPTH_COMPONENT16, driDrawPriv);
1529 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base);
1530 depth->has_surface = screen->depthHasSurface;
1531 }
1532
1533 _mesa_add_soft_renderbuffers(&rfb->base,
1534 GL_FALSE, /* color */
1535 swDepth,
1536 swStencil,
1537 swAccum,
1538 swAlpha,
1539 GL_FALSE /* aux */);
1540 driDrawPriv->driverPrivate = (void *) rfb;
1541
1542 return (driDrawPriv->driverPrivate != NULL);
1543 }
1544
1545
1546 static void radeon_cleanup_renderbuffers(struct radeon_framebuffer *rfb)
1547 {
1548 struct radeon_renderbuffer *rb;
1549
1550 rb = rfb->color_rb[0];
1551 if (rb && rb->bo) {
1552 radeon_bo_unref(rb->bo);
1553 rb->bo = NULL;
1554 }
1555 rb = rfb->color_rb[1];
1556 if (rb && rb->bo) {
1557 radeon_bo_unref(rb->bo);
1558 rb->bo = NULL;
1559 }
1560 rb = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH);
1561 if (rb && rb->bo) {
1562 radeon_bo_unref(rb->bo);
1563 rb->bo = NULL;
1564 }
1565 }
1566
1567 void
1568 radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv)
1569 {
1570 struct radeon_framebuffer *rfb;
1571 if (!driDrawPriv)
1572 return;
1573
1574 rfb = (void*)driDrawPriv->driverPrivate;
1575 if (!rfb)
1576 return;
1577 radeon_cleanup_renderbuffers(rfb);
1578 _mesa_reference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)), NULL);
1579 }
1580
1581 /**
1582 * Choose the appropriate CreateContext function based on the chipset.
1583 * Eventually, all drivers will go through this process.
1584 */
1585 static GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
1586 __DRIcontextPrivate * driContextPriv,
1587 void *sharedContextPriv)
1588 {
1589 __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
1590 radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
1591 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1592 if (IS_R300_CLASS(screen))
1593 return r300CreateContext(glVisual, driContextPriv, sharedContextPriv);
1594 #endif
1595
1596 #if !RADEON_COMMON
1597 (void)screen;
1598 return r100CreateContext(glVisual, driContextPriv, sharedContextPriv);
1599 #endif
1600 return GL_FALSE;
1601 }
1602
1603
1604 /**
1605 * This is the driver specific part of the createNewScreen entry point.
1606 *
1607 * \todo maybe fold this into intelInitDriver
1608 *
1609 * \return the __GLcontextModes supported by this driver
1610 */
1611 static const __DRIconfig **
1612 radeonInitScreen(__DRIscreenPrivate *psp)
1613 {
1614 #if !RADEON_COMMON
1615 static const char *driver_name = "Radeon";
1616 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1617 static const __DRIversion dri_expected = { 4, 0, 0 };
1618 static const __DRIversion drm_expected = { 1, 6, 0 };
1619 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1620 static const char *driver_name = "R200";
1621 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1622 static const __DRIversion dri_expected = { 4, 0, 0 };
1623 static const __DRIversion drm_expected = { 1, 6, 0 };
1624 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1625 static const char *driver_name = "R300";
1626 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1627 static const __DRIversion dri_expected = { 4, 0, 0 };
1628 static const __DRIversion drm_expected = { 1, 24, 0 };
1629 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
1630 static const char *driver_name = "R600";
1631 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1632 static const __DRIversion dri_expected = { 4, 0, 0 };
1633 static const __DRIversion drm_expected = { 1, 24, 0 };
1634 #endif
1635 RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
1636
1637 if ( ! driCheckDriDdxDrmVersions3( driver_name,
1638 &psp->dri_version, & dri_expected,
1639 &psp->ddx_version, & ddx_expected,
1640 &psp->drm_version, & drm_expected ) ) {
1641 return NULL;
1642 }
1643
1644 /* Calling driInitExtensions here, with a NULL context pointer,
1645 * does not actually enable the extensions. It just makes sure
1646 * that all the dispatch offsets for all the extensions that
1647 * *might* be enables are known. This is needed because the
1648 * dispatch offsets need to be known when _mesa_context_create
1649 * is called, but we can't enable the extensions until we have a
1650 * context pointer.
1651 *
1652 * Hello chicken. Hello egg. How are you two today?
1653 */
1654 driInitExtensions( NULL, card_extensions, GL_FALSE );
1655 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1656 driInitExtensions( NULL, blend_extensions, GL_FALSE );
1657 driInitSingleExtension( NULL, ARB_vp_extension );
1658 driInitSingleExtension( NULL, NV_vp_extension );
1659 driInitSingleExtension( NULL, ATI_fs_extension );
1660 driInitExtensions( NULL, point_extensions, GL_FALSE );
1661 #elif (defined(RADEON_COMMON_FOR_R300) || defined(RADEON_COMMON_FOR_R600))
1662 driInitSingleExtension( NULL, gl_20_extension );
1663 #endif
1664
1665 if (!radeonInitDriver(psp))
1666 return NULL;
1667
1668 /* for now fill in all modes */
1669 return radeonFillInModes( psp,
1670 dri_priv->bpp,
1671 (dri_priv->bpp == 16) ? 16 : 24,
1672 (dri_priv->bpp == 16) ? 0 : 8, 1);
1673 }
1674 #define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0]))
1675
1676 /**
1677 * This is the driver specific part of the createNewScreen entry point.
1678 * Called when using DRI2.
1679 *
1680 * \return the __GLcontextModes supported by this driver
1681 */
1682 static const
1683 __DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp)
1684 {
1685 GLenum fb_format[3];
1686 GLenum fb_type[3];
1687 /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't
1688 * support pageflipping at all.
1689 */
1690 static const GLenum back_buffer_modes[] = {
1691 GLX_NONE, GLX_SWAP_UNDEFINED_OML, /*, GLX_SWAP_COPY_OML*/
1692 };
1693 uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1];
1694 int color;
1695 __DRIconfig **configs = NULL;
1696
1697 /* Calling driInitExtensions here, with a NULL context pointer,
1698 * does not actually enable the extensions. It just makes sure
1699 * that all the dispatch offsets for all the extensions that
1700 * *might* be enables are known. This is needed because the
1701 * dispatch offsets need to be known when _mesa_context_create
1702 * is called, but we can't enable the extensions until we have a
1703 * context pointer.
1704 *
1705 * Hello chicken. Hello egg. How are you two today?
1706 */
1707 driInitExtensions( NULL, card_extensions, GL_FALSE );
1708 driInitExtensions( NULL, mm_extensions, GL_FALSE );
1709 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1710 driInitExtensions( NULL, blend_extensions, GL_FALSE );
1711 driInitSingleExtension( NULL, ARB_vp_extension );
1712 driInitSingleExtension( NULL, NV_vp_extension );
1713 driInitSingleExtension( NULL, ATI_fs_extension );
1714 driInitExtensions( NULL, point_extensions, GL_FALSE );
1715 #endif
1716
1717 if (!radeonInitDriver(psp)) {
1718 return NULL;
1719 }
1720 depth_bits[0] = 0;
1721 stencil_bits[0] = 0;
1722 depth_bits[1] = 16;
1723 stencil_bits[1] = 0;
1724 depth_bits[2] = 24;
1725 stencil_bits[2] = 0;
1726 depth_bits[3] = 24;
1727 stencil_bits[3] = 8;
1728
1729 msaa_samples_array[0] = 0;
1730
1731 fb_format[0] = GL_RGB;
1732 fb_type[0] = GL_UNSIGNED_SHORT_5_6_5;
1733
1734 fb_format[1] = GL_BGR;
1735 fb_type[1] = GL_UNSIGNED_INT_8_8_8_8_REV;
1736
1737 fb_format[2] = GL_BGRA;
1738 fb_type[2] = GL_UNSIGNED_INT_8_8_8_8_REV;
1739
1740 for (color = 0; color < ARRAY_SIZE(fb_format); color++) {
1741 __DRIconfig **new_configs;
1742
1743 new_configs = driCreateConfigs(fb_format[color], fb_type[color],
1744 depth_bits,
1745 stencil_bits,
1746 ARRAY_SIZE(depth_bits),
1747 back_buffer_modes,
1748 ARRAY_SIZE(back_buffer_modes),
1749 msaa_samples_array,
1750 ARRAY_SIZE(msaa_samples_array));
1751 if (configs == NULL)
1752 configs = new_configs;
1753 else
1754 configs = driConcatConfigs(configs, new_configs);
1755 }
1756
1757 if (configs == NULL) {
1758 fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__,
1759 __LINE__);
1760 return NULL;
1761 }
1762
1763 return (const __DRIconfig **)configs;
1764 }
1765
1766 /**
1767 * Get information about previous buffer swaps.
1768 */
1769 static int
1770 getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
1771 {
1772 struct radeon_framebuffer *rfb;
1773
1774 if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
1775 || (dPriv->driContextPriv->driverPrivate == NULL)
1776 || (sInfo == NULL) ) {
1777 return -1;
1778 }
1779
1780 rfb = dPriv->driverPrivate;
1781 sInfo->swap_count = rfb->swap_count;
1782 sInfo->swap_ust = rfb->swap_ust;
1783 sInfo->swap_missed_count = rfb->swap_missed_count;
1784
1785 sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
1786 ? driCalculateSwapUsage( dPriv, 0, rfb->swap_missed_ust )
1787 : 0.0;
1788
1789 return 0;
1790 }
1791
1792 const struct __DriverAPIRec driDriverAPI = {
1793 .InitScreen = radeonInitScreen,
1794 .DestroyScreen = radeonDestroyScreen,
1795 #if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1796 .CreateContext = r200CreateContext,
1797 .DestroyContext = r200DestroyContext,
1798 #elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R600)
1799 .CreateContext = r600CreateContext,
1800 .DestroyContext = radeonDestroyContext,
1801 #else
1802 .CreateContext = radeonCreateContext,
1803 .DestroyContext = radeonDestroyContext,
1804 #endif
1805 .CreateBuffer = radeonCreateBuffer,
1806 .DestroyBuffer = radeonDestroyBuffer,
1807 .SwapBuffers = radeonSwapBuffers,
1808 .MakeCurrent = radeonMakeCurrent,
1809 .UnbindContext = radeonUnbindContext,
1810 .GetSwapInfo = getSwapInfo,
1811 .GetDrawableMSC = driDrawableGetMSC32,
1812 .WaitForMSC = driWaitForMSC32,
1813 .WaitForSBC = NULL,
1814 .SwapBuffersMSC = NULL,
1815 .CopySubBuffer = radeonCopySubBuffer,
1816 /* DRI2 */
1817 .InitScreen2 = radeonInitScreen2,
1818 };
1819