ruby: Add support for address ranges in the directory
authorNikos Nikoleris <nikos.nikoleris@arm.com>
Mon, 13 Mar 2017 18:19:08 +0000 (18:19 +0000)
committerNikos Nikoleris <nikos.nikoleris@arm.com>
Tue, 13 Jun 2017 15:52:32 +0000 (15:52 +0000)
commit12db50c89584938839e035da47d206250cbfd7c2
tree831a4151b29cdc14958b8dab2cce97fc3136d7b6
parentdd3fc1f996679f4cfd29f980d43a0652542e6d9b
ruby: Add support for address ranges in the directory

Previously the directory covered a flat address range that always
started from address 0. This change adds a vector of address ranges
with interleaving and hashing that each directory keeps track of and
the necessary flexibility to support systems with non continuous
memory ranges.

Change-Id: I6ea1c629bdf4c5137b7d9c89dbaf6c826adfd977
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2903
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
45 files changed:
configs/ruby/GPU_RfO.py
configs/ruby/Garnet_standalone.py
configs/ruby/MESI_Three_Level.py
configs/ruby/MESI_Two_Level.py
configs/ruby/MI_example.py
configs/ruby/MOESI_AMD_Base.py
configs/ruby/MOESI_CMP_directory.py
configs/ruby/MOESI_CMP_token.py
configs/ruby/MOESI_hammer.py
configs/ruby/Ruby.py
src/base/addr_range.hh
src/mem/protocol/GPU_RfO-TCCdir.sm
src/mem/protocol/GPU_VIPER-TCC.sm
src/mem/protocol/GPU_VIPER_Region-TCC.sm
src/mem/protocol/Garnet_standalone-cache.sm
src/mem/protocol/MESI_Two_Level-L2cache.sm
src/mem/protocol/MESI_Two_Level-dma.sm
src/mem/protocol/MI_example-cache.sm
src/mem/protocol/MI_example-dma.sm
src/mem/protocol/MOESI_AMD_Base-CorePair.sm
src/mem/protocol/MOESI_AMD_Base-L3cache.sm
src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm
src/mem/protocol/MOESI_AMD_Base-Region-dir.sm
src/mem/protocol/MOESI_AMD_Base-RegionBuffer.sm
src/mem/protocol/MOESI_AMD_Base-RegionDir.sm
src/mem/protocol/MOESI_AMD_Base-probeFilter.sm
src/mem/protocol/MOESI_CMP_directory-L2cache.sm
src/mem/protocol/MOESI_CMP_directory-dma.sm
src/mem/protocol/MOESI_CMP_token-L1cache.sm
src/mem/protocol/MOESI_CMP_token-L2cache.sm
src/mem/protocol/MOESI_CMP_token-dir.sm
src/mem/protocol/MOESI_CMP_token-dma.sm
src/mem/protocol/MOESI_hammer-cache.sm
src/mem/protocol/MOESI_hammer-dma.sm
src/mem/protocol/RubySlicc_ComponentMapping.sm
src/mem/ruby/network/Network.cc
src/mem/ruby/network/Network.hh
src/mem/ruby/slicc_interface/AbstractController.cc
src/mem/ruby/slicc_interface/AbstractController.hh
src/mem/ruby/slicc_interface/Controller.py
src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
src/mem/ruby/structures/DirectoryMemory.cc
src/mem/ruby/structures/DirectoryMemory.hh
src/mem/ruby/structures/DirectoryMemory.py
src/mem/slicc/symbols/Type.py