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1 /*

4 *

5 * Permission is hereby granted, free of charge, to any person obtaining a

6 * copy of this software and associated documentation files (the "Software"),

7 * to deal in the Software without restriction, including without limitation

8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

9 * and/or sell copies of the Software, and to permit persons to whom the

10 * Software is furnished to do so, subject to the following conditions:

11 *

12 * The above copyright notice and this permission notice (including the next

13 * paragraph) shall be included in all copies or substantial portions of the

14 * Software.

15 *

16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS

22 * IN THE SOFTWARE.

23 */

25 #include <inttypes.h>

26 #include "pipe/p_state.h"

27 #include "util/u_format.h"

28 #include "util/u_hash.h"

29 #include "util/u_memory.h"

30 #include "util/u_pack_color.h"

31 #include "util/format_srgb.h"

32 #include "util/ralloc.h"

33 #include "util/hash_table.h"

34 #include "tgsi/tgsi_dump.h"

35 #include "tgsi/tgsi_info.h"

36 #include "tgsi/tgsi_lowering.h"

38 #include "vc4_context.h"

39 #include "vc4_qpu.h"

40 #include "vc4_qir.h"

41 #ifdef USE_VC4_SIMULATOR

42 #include "simpenrose/simpenrose.h"

43 #endif

45 struct vc4_key {

46 struct vc4_uncompiled_shader *shader_state;

47 struct {

48 enum pipe_format format;

49 unsigned compare_mode:1;

50 unsigned compare_func:3;

51 unsigned wrap_s:3;

52 unsigned wrap_t:3;

53 uint8_t swizzle[4];

54 } tex[VC4_MAX_TEXTURE_SAMPLERS];

55 uint8_t ucp_enables;

56 };

58 struct vc4_fs_key {

59 struct vc4_key base;

60 enum pipe_format color_format;

61 bool depth_enabled;

62 bool stencil_enabled;

63 bool stencil_twoside;

64 bool stencil_full_writemasks;

65 bool is_points;

66 bool is_lines;

67 bool alpha_test;

68 bool point_coord_upper_left;

69 bool light_twoside;

70 uint8_t alpha_test_func;

71 uint8_t logicop_func;

72 uint32_t point_sprite_mask;

74 struct pipe_rt_blend_state blend;

75 };

77 struct vc4_vs_key {

78 struct vc4_key base;

80 /**

81 * This is a proxy for the array of FS input semantics, which is

82 * larger than we would want to put in the key.

83 */

84 uint64_t compiled_fs_id;

86 enum pipe_format attr_formats[8];

87 bool is_coord;

88 bool per_vertex_point_size;

89 };

91 static void

92 resize_qreg_array(struct vc4_compile *c,

93 struct qreg **regs,

94 uint32_t *size,

95 uint32_t decl_size)

96 {

97 if (*size >= decl_size)

98 return;

100 uint32_t old_size = *size;

101 *size = MAX2(*size * 2, decl_size);

102 *regs = reralloc(c, *regs, struct qreg, *size);

103 if (!*regs) {

104 fprintf(stderr, "Malloc failure\n");

105 abort();

106 }

107

108 for (uint32_t i = old_size; i < *size; i++)

109 (*regs)[i] = c->undef;

110 }

111

112 static struct qreg

113 add_uniform(struct vc4_compile *c,

114 enum quniform_contents contents,

115 uint32_t data)

116 {

117 for (int i = 0; i < c->num_uniforms; i++) {

118 if (c->uniform_contents[i] == contents &&

119 c->uniform_data[i] == data) {

120 return (struct qreg) { QFILE_UNIF, i };

121 }

122 }

123

124 uint32_t uniform = c->num_uniforms++;

125 struct qreg u = { QFILE_UNIF, uniform };

126

127 if (uniform >= c->uniform_array_size) {

128 c->uniform_array_size = MAX2(MAX2(16, uniform + 1),

129 c->uniform_array_size * 2);

130

131 c->uniform_data = reralloc(c, c->uniform_data,

132 uint32_t,

133 c->uniform_array_size);

134 c->uniform_contents = reralloc(c, c->uniform_contents,

135 enum quniform_contents,

136 c->uniform_array_size);

137 }

138

139 c->uniform_contents[uniform] = contents;

140 c->uniform_data[uniform] = data;

141

142 return u;

143 }

144

145 static struct qreg

146 get_temp_for_uniform(struct vc4_compile *c, enum quniform_contents contents,

147 uint32_t data)

148 {

149 struct qreg u = add_uniform(c, contents, data);

150 struct qreg t = qir_MOV(c, u);

151 return t;

152 }

153

154 static struct qreg

155 qir_uniform_ui(struct vc4_compile *c, uint32_t ui)

156 {

157 return get_temp_for_uniform(c, QUNIFORM_CONSTANT, ui);

158 }

159

160 static struct qreg

161 qir_uniform_f(struct vc4_compile *c, float f)

162 {

163 return qir_uniform_ui(c, fui(f));

164 }

165

166 static struct qreg

167 indirect_uniform_load(struct vc4_compile *c,

168 struct tgsi_full_src_register *src, int swiz)

169 {

170 struct tgsi_ind_register *indirect = &src->Indirect;

171 struct vc4_compiler_ubo_range *range = &c->ubo_ranges[indirect->ArrayID];

172 if (!range->used) {

173 range->used = true;

174 range->dst_offset = c->next_ubo_dst_offset;

175 c->next_ubo_dst_offset += range->size;

176 c->num_ubo_ranges++;

177 };

178

179 assert(src->Register.Indirect);

180 assert(indirect->File == TGSI_FILE_ADDRESS);

181

182 struct qreg addr_val = c->addr[indirect->Swizzle];

183 struct qreg indirect_offset =

184 qir_ADD(c, addr_val, qir_uniform_ui(c,

185 range->dst_offset +

186 (src->Register.Index * 16)+

187 swiz * 4));

188 indirect_offset = qir_MIN(c, indirect_offset, qir_uniform_ui(c, (range->dst_offset +

189 range->size - 4)));

190

191 qir_TEX_DIRECT(c, indirect_offset, add_uniform(c, QUNIFORM_UBO_ADDR, 0));

192 struct qreg r4 = qir_TEX_RESULT(c);

193 c->num_texture_samples++;

194 return qir_MOV(c, r4);

195 }

196

197 static struct qreg

198 get_src(struct vc4_compile *c, unsigned tgsi_op,

199 struct tgsi_full_src_register *full_src, int i)

200 {

201 struct tgsi_src_register *src = &full_src->Register;

202 struct qreg r = c->undef;

203

204 uint32_t s = i;

205 switch (i) {

206 case TGSI_SWIZZLE_X:

207 s = src->SwizzleX;

208 break;

209 case TGSI_SWIZZLE_Y:

210 s = src->SwizzleY;

211 break;

212 case TGSI_SWIZZLE_Z:

213 s = src->SwizzleZ;

214 break;

215 case TGSI_SWIZZLE_W:

216 s = src->SwizzleW;

217 break;

218 default:

219 abort();

220 }

221

222 switch (src->File) {

223 case TGSI_FILE_NULL:

224 return r;

225 case TGSI_FILE_TEMPORARY:

226 r = c->temps[src->Index * 4 + s];

227 break;

228 case TGSI_FILE_IMMEDIATE:

229 r = c->consts[src->Index * 4 + s];

230 break;

231 case TGSI_FILE_CONSTANT:

232 if (src->Indirect) {

233 r = indirect_uniform_load(c, full_src, s);

234 } else {

235 r = get_temp_for_uniform(c, QUNIFORM_UNIFORM,

236 src->Index * 4 + s);

237 }

238 break;

239 case TGSI_FILE_INPUT:

240 r = c->inputs[src->Index * 4 + s];

241 break;

242 case TGSI_FILE_SAMPLER:

243 case TGSI_FILE_SAMPLER_VIEW:

244 r = c->undef;

245 break;

246 default:

247 fprintf(stderr, "unknown src file %d\n", src->File);

248 abort();

249 }

250

251 if (src->Absolute)

252 r = qir_FMAXABS(c, r, r);

253

254 if (src->Negate) {

255 switch (tgsi_opcode_infer_src_type(tgsi_op)) {

256 case TGSI_TYPE_SIGNED:

257 case TGSI_TYPE_UNSIGNED:

258 r = qir_SUB(c, qir_uniform_ui(c, 0), r);

259 break;

260 default:

261 r = qir_FSUB(c, qir_uniform_f(c, 0.0), r);

262 break;

263 }

264 }

265

266 return r;

267 };

268

269

270 static void

271 update_dst(struct vc4_compile *c, struct tgsi_full_instruction *tgsi_inst,

272 int i, struct qreg val)

273 {

274 struct tgsi_dst_register *tgsi_dst = &tgsi_inst->Dst[0].Register;

275

276 assert(!tgsi_dst->Indirect);

277

278 switch (tgsi_dst->File) {

279 case TGSI_FILE_TEMPORARY:

280 c->temps[tgsi_dst->Index * 4 + i] = val;

281 break;

282 case TGSI_FILE_OUTPUT:

283 c->outputs[tgsi_dst->Index * 4 + i] = val;

284 c->num_outputs = MAX2(c->num_outputs,

285 tgsi_dst->Index * 4 + i + 1);

286 break;

287 case TGSI_FILE_ADDRESS:

288 assert(tgsi_dst->Index == 0);

289 c->addr[i] = val;

290 break;

291 default:

292 fprintf(stderr, "unknown dst file %d\n", tgsi_dst->File);

293 abort();

294 }

295 };

296

297 static struct qreg

298 get_swizzled_channel(struct vc4_compile *c,

299 struct qreg *srcs, int swiz)

300 {

301 switch (swiz) {

302 default:

303 case UTIL_FORMAT_SWIZZLE_NONE:

304 fprintf(stderr, "warning: unknown swizzle\n");

305 /* FALLTHROUGH */

306 case UTIL_FORMAT_SWIZZLE_0:

307 return qir_uniform_f(c, 0.0);

308 case UTIL_FORMAT_SWIZZLE_1:

309 return qir_uniform_f(c, 1.0);

310 case UTIL_FORMAT_SWIZZLE_X:

311 case UTIL_FORMAT_SWIZZLE_Y:

312 case UTIL_FORMAT_SWIZZLE_Z:

313 case UTIL_FORMAT_SWIZZLE_W:

314 return srcs[swiz];

315 }

316 }

317

318 static struct qreg

319 tgsi_to_qir_alu(struct vc4_compile *c,

320 struct tgsi_full_instruction *tgsi_inst,

321 enum qop op, struct qreg *src, int i)

322 {

323 struct qreg dst = qir_get_temp(c);

324 qir_emit(c, qir_inst4(op, dst,

325 src[0 * 4 + i],

326 src[1 * 4 + i],

327 src[2 * 4 + i],

328 c->undef));

329 return dst;

330 }

331

332 static struct qreg

333 tgsi_to_qir_scalar(struct vc4_compile *c,

334 struct tgsi_full_instruction *tgsi_inst,

335 enum qop op, struct qreg *src, int i)

336 {

337 struct qreg dst = qir_get_temp(c);

338 qir_emit(c, qir_inst(op, dst,

339 src[0 * 4 + 0],

340 c->undef));

341 return dst;

342 }

343

344 static struct qreg

345 tgsi_to_qir_rcp(struct vc4_compile *c,

346 struct tgsi_full_instruction *tgsi_inst,

347 enum qop op, struct qreg *src, int i)

348 {

349 struct qreg x = src[0 * 4 + 0];

350 struct qreg r = qir_RCP(c, x);

351

352 /* Apply a Newton-Raphson step to improve the accuracy. */

353 r = qir_FMUL(c, r, qir_FSUB(c,

354 qir_uniform_f(c, 2.0),

355 qir_FMUL(c, x, r)));

356

357 return r;

358 }

359

360 static struct qreg

361 tgsi_to_qir_rsq(struct vc4_compile *c,

362 struct tgsi_full_instruction *tgsi_inst,

363 enum qop op, struct qreg *src, int i)

364 {

365 struct qreg x = src[0 * 4 + 0];

366 struct qreg r = qir_RSQ(c, x);

367

368 /* Apply a Newton-Raphson step to improve the accuracy. */

369 r = qir_FMUL(c, r, qir_FSUB(c,

370 qir_uniform_f(c, 1.5),

371 qir_FMUL(c,

372 qir_uniform_f(c, 0.5),

373 qir_FMUL(c, x,

374 qir_FMUL(c, r, r)))));

375

376 return r;

377 }

378

379 static struct qreg

380 qir_srgb_decode(struct vc4_compile *c, struct qreg srgb)

381 {

382 struct qreg low = qir_FMUL(c, srgb, qir_uniform_f(c, 1.0 / 12.92));

383 struct qreg high = qir_POW(c,

384 qir_FMUL(c,

385 qir_FADD(c,

386 srgb,

387 qir_uniform_f(c, 0.055)),

388 qir_uniform_f(c, 1.0 / 1.055)),

389 qir_uniform_f(c, 2.4));

390

391 qir_SF(c, qir_FSUB(c, srgb, qir_uniform_f(c, 0.04045)));

392 return qir_SEL_X_Y_NS(c, low, high);

393 }

394

395 static struct qreg

396 qir_srgb_encode(struct vc4_compile *c, struct qreg linear)

397 {

398 struct qreg low = qir_FMUL(c, linear, qir_uniform_f(c, 12.92));

399 struct qreg high = qir_FSUB(c,

400 qir_FMUL(c,

401 qir_uniform_f(c, 1.055),

402 qir_POW(c,

403 linear,

404 qir_uniform_f(c, 0.41666))),

405 qir_uniform_f(c, 0.055));

406

407 qir_SF(c, qir_FSUB(c, linear, qir_uniform_f(c, 0.0031308)));

408 return qir_SEL_X_Y_NS(c, low, high);

409 }

410

411 static struct qreg

412 tgsi_to_qir_umul(struct vc4_compile *c,

413 struct tgsi_full_instruction *tgsi_inst,

414 enum qop op, struct qreg *src, int i)

415 {

416 struct qreg src0_hi = qir_SHR(c, src[0 * 4 + i],

417 qir_uniform_ui(c, 16));

418 struct qreg src0_lo = qir_AND(c, src[0 * 4 + i],

419 qir_uniform_ui(c, 0xffff));

420 struct qreg src1_hi = qir_SHR(c, src[1 * 4 + i],

421 qir_uniform_ui(c, 16));

422 struct qreg src1_lo = qir_AND(c, src[1 * 4 + i],

423 qir_uniform_ui(c, 0xffff));

424

425 struct qreg hilo = qir_MUL24(c, src0_hi, src1_lo);

426 struct qreg lohi = qir_MUL24(c, src0_lo, src1_hi);

427 struct qreg lolo = qir_MUL24(c, src0_lo, src1_lo);

428

429 return qir_ADD(c, lolo, qir_SHL(c,

430 qir_ADD(c, hilo, lohi),

431 qir_uniform_ui(c, 16)));

432 }

433

434 static struct qreg

435 tgsi_to_qir_umad(struct vc4_compile *c,

436 struct tgsi_full_instruction *tgsi_inst,

437 enum qop op, struct qreg *src, int i)

438 {

439 return qir_ADD(c, tgsi_to_qir_umul(c, NULL, 0, src, i), src[2 * 4 + i]);

440 }

441

442 static struct qreg

443 tgsi_to_qir_idiv(struct vc4_compile *c,

444 struct tgsi_full_instruction *tgsi_inst,

445 enum qop op, struct qreg *src, int i)

446 {

447 return qir_FTOI(c, qir_FMUL(c,

448 qir_ITOF(c, src[0 * 4 + i]),

449 qir_RCP(c, qir_ITOF(c, src[1 * 4 + i]))));

450 }

451

452 static struct qreg

453 tgsi_to_qir_ineg(struct vc4_compile *c,

454 struct tgsi_full_instruction *tgsi_inst,

455 enum qop op, struct qreg *src, int i)

456 {

457 return qir_SUB(c, qir_uniform_ui(c, 0), src[0 * 4 + i]);

458 }

459

460 static struct qreg

461 tgsi_to_qir_seq(struct vc4_compile *c,

462 struct tgsi_full_instruction *tgsi_inst,

463 enum qop op, struct qreg *src, int i)

464 {

465 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));

466 return qir_SEL_X_0_ZS(c, qir_uniform_f(c, 1.0));

467 }

468

469 static struct qreg

470 tgsi_to_qir_sne(struct vc4_compile *c,

471 struct tgsi_full_instruction *tgsi_inst,

472 enum qop op, struct qreg *src, int i)

473 {

474 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));

475 return qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0));

476 }

477

478 static struct qreg

479 tgsi_to_qir_slt(struct vc4_compile *c,

480 struct tgsi_full_instruction *tgsi_inst,

481 enum qop op, struct qreg *src, int i)

482 {

483 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));

484 return qir_SEL_X_0_NS(c, qir_uniform_f(c, 1.0));

485 }

486

487 static struct qreg

488 tgsi_to_qir_sge(struct vc4_compile *c,

489 struct tgsi_full_instruction *tgsi_inst,

490 enum qop op, struct qreg *src, int i)

491 {

492 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));

493 return qir_SEL_X_0_NC(c, qir_uniform_f(c, 1.0));

494 }

495

496 static struct qreg

497 tgsi_to_qir_fseq(struct vc4_compile *c,

498 struct tgsi_full_instruction *tgsi_inst,

499 enum qop op, struct qreg *src, int i)

500 {

501 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));

502 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));

503 }

504

505 static struct qreg

506 tgsi_to_qir_fsne(struct vc4_compile *c,

507 struct tgsi_full_instruction *tgsi_inst,

508 enum qop op, struct qreg *src, int i)

509 {

510 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));

511 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));

512 }

513

514 static struct qreg

515 tgsi_to_qir_fslt(struct vc4_compile *c,

516 struct tgsi_full_instruction *tgsi_inst,

517 enum qop op, struct qreg *src, int i)

518 {

519 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));

520 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));

521 }

522

523 static struct qreg

524 tgsi_to_qir_fsge(struct vc4_compile *c,

525 struct tgsi_full_instruction *tgsi_inst,

526 enum qop op, struct qreg *src, int i)

527 {

528 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], src[1 * 4 + i]));

529 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));

530 }

531

532 static struct qreg

533 tgsi_to_qir_useq(struct vc4_compile *c,

534 struct tgsi_full_instruction *tgsi_inst,

535 enum qop op, struct qreg *src, int i)

536 {

537 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));

538 return qir_SEL_X_0_ZS(c, qir_uniform_ui(c, ~0));

539 }

540

541 static struct qreg

542 tgsi_to_qir_usne(struct vc4_compile *c,

543 struct tgsi_full_instruction *tgsi_inst,

544 enum qop op, struct qreg *src, int i)

545 {

546 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));

547 return qir_SEL_X_0_ZC(c, qir_uniform_ui(c, ~0));

548 }

549

550 static struct qreg

551 tgsi_to_qir_islt(struct vc4_compile *c,

552 struct tgsi_full_instruction *tgsi_inst,

553 enum qop op, struct qreg *src, int i)

554 {

555 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));

556 return qir_SEL_X_0_NS(c, qir_uniform_ui(c, ~0));

557 }

558

559 static struct qreg

560 tgsi_to_qir_isge(struct vc4_compile *c,

561 struct tgsi_full_instruction *tgsi_inst,

562 enum qop op, struct qreg *src, int i)

563 {

564 qir_SF(c, qir_SUB(c, src[0 * 4 + i], src[1 * 4 + i]));

565 return qir_SEL_X_0_NC(c, qir_uniform_ui(c, ~0));

566 }

567

568 static struct qreg

569 tgsi_to_qir_cmp(struct vc4_compile *c,

570 struct tgsi_full_instruction *tgsi_inst,

571 enum qop op, struct qreg *src, int i)

572 {

573 qir_SF(c, src[0 * 4 + i]);

574 return qir_SEL_X_Y_NS(c,

575 src[1 * 4 + i],

576 src[2 * 4 + i]);

577 }

578

579 static struct qreg

580 tgsi_to_qir_ucmp(struct vc4_compile *c,

581 struct tgsi_full_instruction *tgsi_inst,

582 enum qop op, struct qreg *src, int i)

583 {

584 qir_SF(c, src[0 * 4 + i]);

585 return qir_SEL_X_Y_ZC(c,

586 src[1 * 4 + i],

587 src[2 * 4 + i]);

588 }

589

590 static struct qreg

591 tgsi_to_qir_mad(struct vc4_compile *c,

592 struct tgsi_full_instruction *tgsi_inst,

593 enum qop op, struct qreg *src, int i)

594 {

595 return qir_FADD(c,

596 qir_FMUL(c,

597 src[0 * 4 + i],

598 src[1 * 4 + i]),

599 src[2 * 4 + i]);

600 }

601

602 static struct qreg

603 tgsi_to_qir_lrp(struct vc4_compile *c,

604 struct tgsi_full_instruction *tgsi_inst,

605 enum qop op, struct qreg *src, int i)

606 {

607 struct qreg src0 = src[0 * 4 + i];

608 struct qreg src1 = src[1 * 4 + i];

609 struct qreg src2 = src[2 * 4 + i];

610

611 /* LRP is:

612 * src0 * src1 + (1 - src0) * src2.

613 * -> src0 * src1 + src2 - src0 * src2

614 * -> src2 + src0 * (src1 - src2)

615 */

616 return qir_FADD(c, src2, qir_FMUL(c, src0, qir_FSUB(c, src1, src2)));

617

618 }

619

620 static void

621 tgsi_to_qir_tex(struct vc4_compile *c,

622 struct tgsi_full_instruction *tgsi_inst,

623 enum qop op, struct qreg *src)

624 {

625 assert(!tgsi_inst->Instruction.Saturate);

626

627 struct qreg s = src[0 * 4 + 0];

628 struct qreg t = src[0 * 4 + 1];

629 struct qreg r = src[0 * 4 + 2];

630 uint32_t unit = tgsi_inst->Src[1].Register.Index;

631 bool is_txl = tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL;

632

633 struct qreg proj = c->undef;

634 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP) {

635 proj = qir_RCP(c, src[0 * 4 + 3]);

636 s = qir_FMUL(c, s, proj);

637 t = qir_FMUL(c, t, proj);

638 }

639

640 struct qreg texture_u[] = {

641 add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),

642 add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),

643 add_uniform(c, QUNIFORM_CONSTANT, 0),

644 add_uniform(c, QUNIFORM_CONSTANT, 0),

645 };

646 uint32_t next_texture_u = 0;

647

648 /* There is no native support for GL texture rectangle coordinates, so

649 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,

650 * 1]).

651 */

652 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_RECT ||

653 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {

654 s = qir_FMUL(c, s,

655 get_temp_for_uniform(c,

656 QUNIFORM_TEXRECT_SCALE_X,

657 unit));

658 t = qir_FMUL(c, t,

659 get_temp_for_uniform(c,

660 QUNIFORM_TEXRECT_SCALE_Y,

661 unit));

662 }

663

664 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_CUBE ||

665 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||

666 is_txl) {

667 texture_u[2] = add_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,

668 unit | (is_txl << 16));

669 }

670

671 if (tgsi_inst->Texture.Texture == TGSI_TEXTURE_CUBE ||

672 tgsi_inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE) {

673 struct qreg ma = qir_FMAXABS(c, qir_FMAXABS(c, s, t), r);

674 struct qreg rcp_ma = qir_RCP(c, ma);

675 s = qir_FMUL(c, s, rcp_ma);

676 t = qir_FMUL(c, t, rcp_ma);

677 r = qir_FMUL(c, r, rcp_ma);

678

679 qir_TEX_R(c, r, texture_u[next_texture_u++]);

680 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||

681 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||

682 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||

683 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {

684 qir_TEX_R(c, get_temp_for_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR, unit),

685 texture_u[next_texture_u++]);

686 }

687

688 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {

689 s = qir_FMIN(c, qir_FMAX(c, s, qir_uniform_f(c, 0.0)),

690 qir_uniform_f(c, 1.0));

691 }

692

693 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {

694 t = qir_FMIN(c, qir_FMAX(c, t, qir_uniform_f(c, 0.0)),

695 qir_uniform_f(c, 1.0));

696 }

697

698 qir_TEX_T(c, t, texture_u[next_texture_u++]);

699

700 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXB ||

701 tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXL)

702 qir_TEX_B(c, src[0 * 4 + 3], texture_u[next_texture_u++]);

703

704 qir_TEX_S(c, s, texture_u[next_texture_u++]);

705

706 c->num_texture_samples++;

707 struct qreg r4 = qir_TEX_RESULT(c);

708

709 enum pipe_format format = c->key->tex[unit].format;

710

711 struct qreg unpacked[4];

712 if (util_format_is_depth_or_stencil(format)) {

713 struct qreg depthf = qir_ITOF(c, qir_SHR(c, r4,

714 qir_uniform_ui(c, 8)));

715 struct qreg normalized = qir_FMUL(c, depthf,

716 qir_uniform_f(c, 1.0f/0xffffff));

717

718 struct qreg depth_output;

719

720 struct qreg one = qir_uniform_f(c, 1.0f);

721 if (c->key->tex[unit].compare_mode) {

722 struct qreg compare = src[0 * 4 + 2];

723

724 if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_TXP)

725 compare = qir_FMUL(c, compare, proj);

726

727 switch (c->key->tex[unit].compare_func) {

728 case PIPE_FUNC_NEVER:

729 depth_output = qir_uniform_f(c, 0.0f);

730 break;

731 case PIPE_FUNC_ALWAYS:

732 depth_output = one;

733 break;

734 case PIPE_FUNC_EQUAL:

735 qir_SF(c, qir_FSUB(c, compare, normalized));

736 depth_output = qir_SEL_X_0_ZS(c, one);

737 break;

738 case PIPE_FUNC_NOTEQUAL:

739 qir_SF(c, qir_FSUB(c, compare, normalized));

740 depth_output = qir_SEL_X_0_ZC(c, one);

741 break;

742 case PIPE_FUNC_GREATER:

743 qir_SF(c, qir_FSUB(c, compare, normalized));

744 depth_output = qir_SEL_X_0_NC(c, one);

745 break;

746 case PIPE_FUNC_GEQUAL:

747 qir_SF(c, qir_FSUB(c, normalized, compare));

748 depth_output = qir_SEL_X_0_NS(c, one);

749 break;

750 case PIPE_FUNC_LESS:

751 qir_SF(c, qir_FSUB(c, compare, normalized));

752 depth_output = qir_SEL_X_0_NS(c, one);

753 break;

754 case PIPE_FUNC_LEQUAL:

755 qir_SF(c, qir_FSUB(c, normalized, compare));

756 depth_output = qir_SEL_X_0_NC(c, one);

757 break;

758 }

759 } else {

760 depth_output = normalized;

761 }

762

763 for (int i = 0; i < 4; i++)

764 unpacked[i] = depth_output;

765 } else {

766 for (int i = 0; i < 4; i++)

767 unpacked[i] = qir_R4_UNPACK(c, r4, i);

768 }

769

770 const uint8_t *format_swiz = vc4_get_format_swizzle(format);

771 struct qreg texture_output[4];

772 for (int i = 0; i < 4; i++) {

773 texture_output[i] = get_swizzled_channel(c, unpacked,

774 format_swiz[i]);

775 }

776

777 if (util_format_is_srgb(format)) {

778 for (int i = 0; i < 3; i++)

779 texture_output[i] = qir_srgb_decode(c,

780 texture_output[i]);

781 }

782

783 for (int i = 0; i < 4; i++) {

784 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))

785 continue;

786

787 update_dst(c, tgsi_inst, i,

788 get_swizzled_channel(c, texture_output,

789 c->key->tex[unit].swizzle[i]));

790 }

791 }

792

793 static struct qreg

794 tgsi_to_qir_trunc(struct vc4_compile *c,

795 struct tgsi_full_instruction *tgsi_inst,

796 enum qop op, struct qreg *src, int i)

797 {

798 return qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));

799 }

800

801 /**

802 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds

803 * to zero).

804 */

805 static struct qreg

806 tgsi_to_qir_frc(struct vc4_compile *c,

807 struct tgsi_full_instruction *tgsi_inst,

808 enum qop op, struct qreg *src, int i)

809 {

810 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));

811 struct qreg diff = qir_FSUB(c, src[0 * 4 + i], trunc);

812 qir_SF(c, diff);

813 return qir_SEL_X_Y_NS(c,

814 qir_FADD(c, diff, qir_uniform_f(c, 1.0)),

815 diff);

816 }

817

818 /**

819 * Computes floor(x), which is tricky because our FTOI truncates (rounds to

820 * zero).

821 */

822 static struct qreg

823 tgsi_to_qir_flr(struct vc4_compile *c,

824 struct tgsi_full_instruction *tgsi_inst,

825 enum qop op, struct qreg *src, int i)

826 {

827 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));

828

829 /* This will be < 0 if we truncated and the truncation was of a value

830 * that was < 0 in the first place.

831 */

832 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], trunc));

833

834 return qir_SEL_X_Y_NS(c,

835 qir_FSUB(c, trunc, qir_uniform_f(c, 1.0)),

836 trunc);

837 }

838

839 /**

840 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to

841 * zero).

842 */

843 static struct qreg

844 tgsi_to_qir_ceil(struct vc4_compile *c,

845 struct tgsi_full_instruction *tgsi_inst,

846 enum qop op, struct qreg *src, int i)

847 {

848 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src[0 * 4 + i]));

849

850 /* This will be < 0 if we truncated and the truncation was of a value

851 * that was > 0 in the first place.

852 */

853 qir_SF(c, qir_FSUB(c, trunc, src[0 * 4 + i]));

854

855 return qir_SEL_X_Y_NS(c,

856 qir_FADD(c, trunc, qir_uniform_f(c, 1.0)),

857 trunc);

858 }

859

860 static struct qreg

861 tgsi_to_qir_abs(struct vc4_compile *c,

862 struct tgsi_full_instruction *tgsi_inst,

863 enum qop op, struct qreg *src, int i)

864 {

865 struct qreg arg = src[0 * 4 + i];

866 return qir_FMAXABS(c, arg, arg);

867 }

868

869 /* Note that this instruction replicates its result from the x channel */

870 static struct qreg

871 tgsi_to_qir_sin(struct vc4_compile *c,

872 struct tgsi_full_instruction *tgsi_inst,

873 enum qop op, struct qreg *src, int i)

874 {

875 float coeff[] = {

876 -2.0 * M_PI,

877 pow(2.0 * M_PI, 3) / (3 * 2 * 1),

878 -pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),

879 pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),

880 -pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),

881 };

882

883 struct qreg scaled_x =

884 qir_FMUL(c,

885 src[0 * 4 + 0],

886 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));

887

888 struct qreg x = qir_FADD(c,

889 tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0),

890 qir_uniform_f(c, -0.5));

891 struct qreg x2 = qir_FMUL(c, x, x);

892 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));

893 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {

894 x = qir_FMUL(c, x, x2);

895 sum = qir_FADD(c,

896 sum,

897 qir_FMUL(c,

898 x,

899 qir_uniform_f(c, coeff[i])));

900 }

901 return sum;

902 }

903

904 /* Note that this instruction replicates its result from the x channel */

905 static struct qreg

906 tgsi_to_qir_cos(struct vc4_compile *c,

907 struct tgsi_full_instruction *tgsi_inst,

908 enum qop op, struct qreg *src, int i)

909 {

910 float coeff[] = {

911 -1.0f,

912 pow(2.0 * M_PI, 2) / (2 * 1),

913 -pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),

914 pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),

915 -pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),

916 pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),

917 };

918

919 struct qreg scaled_x =

920 qir_FMUL(c, src[0 * 4 + 0],

921 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));

922 struct qreg x_frac = qir_FADD(c,

923 tgsi_to_qir_frc(c, NULL, 0, &scaled_x, 0),

924 qir_uniform_f(c, -0.5));

925

926 struct qreg sum = qir_uniform_f(c, coeff[0]);

927 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);

928 struct qreg x = x2; /* Current x^2, x^4, or x^6 */

929 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {

930 if (i != 1)

931 x = qir_FMUL(c, x, x2);

932

933 struct qreg mul = qir_FMUL(c,

934 x,

935 qir_uniform_f(c, coeff[i]));

936 if (i == 0)

937 sum = mul;

938 else

939 sum = qir_FADD(c, sum, mul);

940 }

941 return sum;

942 }

943

944 static struct qreg

945 tgsi_to_qir_clamp(struct vc4_compile *c,

946 struct tgsi_full_instruction *tgsi_inst,

947 enum qop op, struct qreg *src, int i)

948 {

949 return qir_FMAX(c, qir_FMIN(c,

950 src[0 * 4 + i],

951 src[2 * 4 + i]),

952 src[1 * 4 + i]);

953 }

954

955 static struct qreg

956 tgsi_to_qir_ssg(struct vc4_compile *c,

957 struct tgsi_full_instruction *tgsi_inst,

958 enum qop op, struct qreg *src, int i)

959 {

960 qir_SF(c, src[0 * 4 + i]);

961 return qir_SEL_X_Y_NC(c,

962 qir_SEL_X_0_ZC(c, qir_uniform_f(c, 1.0)),

963 qir_uniform_f(c, -1.0));

964 }

965

966 /* Compare to tgsi_to_qir_flr() for the floor logic. */

967 static struct qreg

968 tgsi_to_qir_arl(struct vc4_compile *c,

969 struct tgsi_full_instruction *tgsi_inst,

970 enum qop op, struct qreg *src, int i)

971 {

972 struct qreg trunc = qir_FTOI(c, src[0 * 4 + i]);

973 struct qreg scaled = qir_SHL(c, trunc, qir_uniform_ui(c, 4));

974

975 qir_SF(c, qir_FSUB(c, src[0 * 4 + i], qir_ITOF(c, trunc)));

976

977 return qir_SEL_X_Y_NS(c, qir_SUB(c, scaled, qir_uniform_ui(c, 4)),

978 scaled);

979 }

980

981 static struct qreg

982 tgsi_to_qir_uarl(struct vc4_compile *c,

983 struct tgsi_full_instruction *tgsi_inst,

984 enum qop op, struct qreg *src, int i)

985 {

986 return qir_SHL(c, src[0 * 4 + i], qir_uniform_ui(c, 4));

987 }

988

989 static void

990 emit_vertex_input(struct vc4_compile *c, int attr)

991 {

992 enum pipe_format format = c->vs_key->attr_formats[attr];

993 struct qreg vpm_reads[4];

994

995 /* Right now, we're setting the VPM offsets to be 16 bytes wide every

996 * time, so we always read 4 32-bit VPM entries.

997 */

998 for (int i = 0; i < 4; i++) {

999 vpm_reads[i] = qir_get_temp(c);

1000 qir_emit(c, qir_inst(QOP_VPM_READ,

1001 vpm_reads[i],

1002 c->undef,

1003 c->undef));

1004 c->num_inputs++;

1005 }

1006

1007 bool format_warned = false;

1008 const struct util_format_description *desc =

1009 util_format_description(format);

1010

1011 for (int i = 0; i < 4; i++) {

1012 uint8_t swiz = desc->swizzle[i];

1013 struct qreg result;

1014

1015 if (swiz > UTIL_FORMAT_SWIZZLE_W)

1016 result = get_swizzled_channel(c, vpm_reads, swiz);

1017 else if (desc->channel[swiz].size == 32 &&

1018 desc->channel[swiz].type == UTIL_FORMAT_TYPE_FLOAT) {

1019 result = get_swizzled_channel(c, vpm_reads, swiz);

1020 } else if (desc->channel[swiz].size == 8 &&

1021 (desc->channel[swiz].type == UTIL_FORMAT_TYPE_UNSIGNED ||

1022 desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED) &&

1023 desc->channel[swiz].normalized) {

1024 struct qreg vpm = vpm_reads[0];

1025 if (desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED)

1026 vpm = qir_XOR(c, vpm, qir_uniform_ui(c, 0x80808080));

1027 result = qir_UNPACK_8(c, vpm, swiz);

1028 } else {

1029 if (!format_warned) {

1030 fprintf(stderr,

1031 "vtx element %d unsupported type: %s\n",

1032 attr, util_format_name(format));

1033 format_warned = true;

1034 }

1035 result = qir_uniform_f(c, 0.0);

1036 }

1037

1038 if (desc->channel[swiz].normalized &&

1039 desc->channel[swiz].type == UTIL_FORMAT_TYPE_SIGNED) {

1040 result = qir_FSUB(c,

1041 qir_FMUL(c,

1042 result,

1043 qir_uniform_f(c, 2.0)),

1044 qir_uniform_f(c, 1.0));

1045 }

1046

1047 c->inputs[attr * 4 + i] = result;

1048 }

1049 }

1050

1051 static void

1052 tgsi_to_qir_kill_if(struct vc4_compile *c, struct qreg *src, int i)

1053 {

1054 if (c->discard.file == QFILE_NULL)

1055 c->discard = qir_uniform_f(c, 0.0);

1056 qir_SF(c, src[0 * 4 + i]);

1057 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_f(c, 1.0),

1058 c->discard);

1059 }

1060

1061 static void

1062 emit_fragcoord_input(struct vc4_compile *c, int attr)

1063 {

1064 c->inputs[attr * 4 + 0] = qir_FRAG_X(c);

1065 c->inputs[attr * 4 + 1] = qir_FRAG_Y(c);

1066 c->inputs[attr * 4 + 2] =

1067 qir_FMUL(c,

1068 qir_ITOF(c, qir_FRAG_Z(c)),

1069 qir_uniform_f(c, 1.0 / 0xffffff));

1070 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));

1071 }

1072

1073 static void

1074 emit_point_coord_input(struct vc4_compile *c, int attr)

1075 {

1076 if (c->point_x.file == QFILE_NULL) {

1077 c->point_x = qir_uniform_f(c, 0.0);

1078 c->point_y = qir_uniform_f(c, 0.0);

1079 }

1080

1081 c->inputs[attr * 4 + 0] = c->point_x;

1082 if (c->fs_key->point_coord_upper_left) {

1083 c->inputs[attr * 4 + 1] = qir_FSUB(c,

1084 qir_uniform_f(c, 1.0),

1085 c->point_y);

1086 } else {

1087 c->inputs[attr * 4 + 1] = c->point_y;

1088 }

1089 c->inputs[attr * 4 + 2] = qir_uniform_f(c, 0.0);

1090 c->inputs[attr * 4 + 3] = qir_uniform_f(c, 1.0);

1091 }

1092

1093 static struct qreg

1094 emit_fragment_varying(struct vc4_compile *c, uint8_t semantic,

1095 uint8_t index, uint8_t swizzle)

1096 {

1097 uint32_t i = c->num_input_semantics++;

1098 struct qreg vary = {

1099 QFILE_VARY,

1100 i

1101 };

1102

1103 if (c->num_input_semantics >= c->input_semantics_array_size) {

1104 c->input_semantics_array_size =

1105 MAX2(4, c->input_semantics_array_size * 2);

1106

1107 c->input_semantics = reralloc(c, c->input_semantics,

1108 struct vc4_varying_semantic,

1109 c->input_semantics_array_size);

1110 }

1111

1112 c->input_semantics[i].semantic = semantic;

1113 c->input_semantics[i].index = index;

1114 c->input_semantics[i].swizzle = swizzle;

1115

1116 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));

1117 }

1118

1119 static void

1120 emit_fragment_input(struct vc4_compile *c, int attr,

1121 struct tgsi_full_declaration *decl)

1122 {

1123 for (int i = 0; i < 4; i++) {

1124 c->inputs[attr * 4 + i] =

1125 emit_fragment_varying(c,

1126 decl->Semantic.Name,

1127 decl->Semantic.Index,

1128 i);

1129 c->num_inputs++;

1130 }

1131 }

1132

1133 static void

1134 emit_face_input(struct vc4_compile *c, int attr)

1135 {

1136 c->inputs[attr * 4 + 0] = qir_FSUB(c,

1137 qir_uniform_f(c, 1.0),

1138 qir_FMUL(c,

1139 qir_ITOF(c, qir_FRAG_REV_FLAG(c)),

1140 qir_uniform_f(c, 2.0)));

1141 c->inputs[attr * 4 + 1] = qir_uniform_f(c, 0.0);

1142 c->inputs[attr * 4 + 2] = qir_uniform_f(c, 0.0);

1143 c->inputs[attr * 4 + 3] = qir_uniform_f(c, 1.0);

1144 }

1145

1146 static void

1147 add_output(struct vc4_compile *c,

1148 uint32_t decl_offset,

1149 uint8_t semantic_name,

1150 uint8_t semantic_index,

1151 uint8_t semantic_swizzle)

1152 {

1153 uint32_t old_array_size = c->outputs_array_size;

1154 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,

1155 decl_offset + 1);

1156

1157 if (old_array_size != c->outputs_array_size) {

1158 c->output_semantics = reralloc(c,

1159 c->output_semantics,

1160 struct vc4_varying_semantic,

1161 c->outputs_array_size);

1162 }

1163

1164 c->output_semantics[decl_offset].semantic = semantic_name;

1165 c->output_semantics[decl_offset].index = semantic_index;

1166 c->output_semantics[decl_offset].swizzle = semantic_swizzle;

1167 }

1168

1169 static void

1170 add_array_info(struct vc4_compile *c, uint32_t array_id,

1171 uint32_t start, uint32_t size)

1172 {

1173 if (array_id >= c->ubo_ranges_array_size) {

1174 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,

1175 array_id + 1);

1176 c->ubo_ranges = reralloc(c, c->ubo_ranges,

1177 struct vc4_compiler_ubo_range,

1178 c->ubo_ranges_array_size);

1179 }

1180

1181 c->ubo_ranges[array_id].dst_offset = 0;

1182 c->ubo_ranges[array_id].src_offset = start;

1183 c->ubo_ranges[array_id].size = size;

1184 c->ubo_ranges[array_id].used = false;

1185 }

1186

1187 static void

1188 emit_tgsi_declaration(struct vc4_compile *c,

1189 struct tgsi_full_declaration *decl)

1190 {

1191 switch (decl->Declaration.File) {

1192 case TGSI_FILE_TEMPORARY: {

1193 uint32_t old_size = c->temps_array_size;

1194 resize_qreg_array(c, &c->temps, &c->temps_array_size,

1195 (decl->Range.Last + 1) * 4);

1196

1197 for (int i = old_size; i < c->temps_array_size; i++)

1198 c->temps[i] = qir_uniform_ui(c, 0);

1199 break;

1200 }

1201

1202 case TGSI_FILE_INPUT:

1203 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,

1204 (decl->Range.Last + 1) * 4);

1205

1206 for (int i = decl->Range.First;

1207 i <= decl->Range.Last;

1208 i++) {

1209 if (c->stage == QSTAGE_FRAG) {

1210 if (decl->Semantic.Name ==

1211 TGSI_SEMANTIC_POSITION) {

1212 emit_fragcoord_input(c, i);

1213 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {

1214 emit_face_input(c, i);

1215 } else if (decl->Semantic.Name == TGSI_SEMANTIC_GENERIC &&

1216 (c->fs_key->point_sprite_mask &

1217 (1 << decl->Semantic.Index))) {

1218 emit_point_coord_input(c, i);

1219 } else {

1220 emit_fragment_input(c, i, decl);

1221 }

1222 } else {

1223 emit_vertex_input(c, i);

1224 }

1225 }

1226 break;

1227

1228 case TGSI_FILE_OUTPUT: {

1229 for (int i = 0; i < 4; i++) {

1230 add_output(c,

1231 decl->Range.First * 4 + i,

1232 decl->Semantic.Name,

1233 decl->Semantic.Index,

1234 i);

1235 }

1236

1237 switch (decl->Semantic.Name) {

1238 case TGSI_SEMANTIC_POSITION:

1239 c->output_position_index = decl->Range.First * 4;

1240 break;

1241 case TGSI_SEMANTIC_CLIPVERTEX:

1242 c->output_clipvertex_index = decl->Range.First * 4;

1243 break;

1244 case TGSI_SEMANTIC_COLOR:

1245 c->output_color_index = decl->Range.First * 4;

1246 break;

1247 case TGSI_SEMANTIC_PSIZE:

1248 c->output_point_size_index = decl->Range.First * 4;

1249 break;

1250 }

1251

1252 break;

1253

1254 case TGSI_FILE_CONSTANT:

1255 add_array_info(c,

1256 decl->Array.ArrayID,

1257 decl->Range.First * 16,

1258 (decl->Range.Last -

1259 decl->Range.First + 1) * 16);

1260 break;

1261 }

1262 }

1263 }

1264

1265 static void

1266 emit_tgsi_instruction(struct vc4_compile *c,

1267 struct tgsi_full_instruction *tgsi_inst)

1268 {

1269 static const struct {

1270 enum qop op;

1271 struct qreg (*func)(struct vc4_compile *c,

1272 struct tgsi_full_instruction *tgsi_inst,

1273 enum qop op,

1274 struct qreg *src, int i);

1275 } op_trans[] = {

1276 [TGSI_OPCODE_MOV] = { QOP_MOV, tgsi_to_qir_alu },

1277 [TGSI_OPCODE_ABS] = { 0, tgsi_to_qir_abs },

1278 [TGSI_OPCODE_MUL] = { QOP_FMUL, tgsi_to_qir_alu },

1279 [TGSI_OPCODE_ADD] = { QOP_FADD, tgsi_to_qir_alu },

1280 [TGSI_OPCODE_SUB] = { QOP_FSUB, tgsi_to_qir_alu },

1281 [TGSI_OPCODE_MIN] = { QOP_FMIN, tgsi_to_qir_alu },

1282 [TGSI_OPCODE_MAX] = { QOP_FMAX, tgsi_to_qir_alu },

1283 [TGSI_OPCODE_F2I] = { QOP_FTOI, tgsi_to_qir_alu },

1284 [TGSI_OPCODE_I2F] = { QOP_ITOF, tgsi_to_qir_alu },

1285 [TGSI_OPCODE_UADD] = { QOP_ADD, tgsi_to_qir_alu },

1286 [TGSI_OPCODE_USHR] = { QOP_SHR, tgsi_to_qir_alu },

1287 [TGSI_OPCODE_ISHR] = { QOP_ASR, tgsi_to_qir_alu },

1288 [TGSI_OPCODE_SHL] = { QOP_SHL, tgsi_to_qir_alu },

1289 [TGSI_OPCODE_IMIN] = { QOP_MIN, tgsi_to_qir_alu },

1290 [TGSI_OPCODE_IMAX] = { QOP_MAX, tgsi_to_qir_alu },

1291 [TGSI_OPCODE_AND] = { QOP_AND, tgsi_to_qir_alu },

1292 [TGSI_OPCODE_OR] = { QOP_OR, tgsi_to_qir_alu },

1293 [TGSI_OPCODE_XOR] = { QOP_XOR, tgsi_to_qir_alu },

1294 [TGSI_OPCODE_NOT] = { QOP_NOT, tgsi_to_qir_alu },

1295

1296 [TGSI_OPCODE_UMUL] = { 0, tgsi_to_qir_umul },

1297 [TGSI_OPCODE_UMAD] = { 0, tgsi_to_qir_umad },

1298 [TGSI_OPCODE_IDIV] = { 0, tgsi_to_qir_idiv },

1299 [TGSI_OPCODE_INEG] = { 0, tgsi_to_qir_ineg },

1300

1301 [TGSI_OPCODE_SEQ] = { 0, tgsi_to_qir_seq },

1302 [TGSI_OPCODE_SNE] = { 0, tgsi_to_qir_sne },

1303 [TGSI_OPCODE_SGE] = { 0, tgsi_to_qir_sge },

1304 [TGSI_OPCODE_SLT] = { 0, tgsi_to_qir_slt },

1305 [TGSI_OPCODE_FSEQ] = { 0, tgsi_to_qir_fseq },

1306 [TGSI_OPCODE_FSNE] = { 0, tgsi_to_qir_fsne },

1307 [TGSI_OPCODE_FSGE] = { 0, tgsi_to_qir_fsge },

1308 [TGSI_OPCODE_FSLT] = { 0, tgsi_to_qir_fslt },

1309 [TGSI_OPCODE_USEQ] = { 0, tgsi_to_qir_useq },

1310 [TGSI_OPCODE_USNE] = { 0, tgsi_to_qir_usne },

1311 [TGSI_OPCODE_ISGE] = { 0, tgsi_to_qir_isge },

1312 [TGSI_OPCODE_ISLT] = { 0, tgsi_to_qir_islt },

1313

1314 [TGSI_OPCODE_CMP] = { 0, tgsi_to_qir_cmp },

1315 [TGSI_OPCODE_UCMP] = { 0, tgsi_to_qir_ucmp },

1316 [TGSI_OPCODE_MAD] = { 0, tgsi_to_qir_mad },

1317 [TGSI_OPCODE_RCP] = { QOP_RCP, tgsi_to_qir_rcp },

1318 [TGSI_OPCODE_RSQ] = { QOP_RSQ, tgsi_to_qir_rsq },

1319 [TGSI_OPCODE_EX2] = { QOP_EXP2, tgsi_to_qir_scalar },

1320 [TGSI_OPCODE_LG2] = { QOP_LOG2, tgsi_to_qir_scalar },

1321 [TGSI_OPCODE_LRP] = { 0, tgsi_to_qir_lrp },

1322 [TGSI_OPCODE_TRUNC] = { 0, tgsi_to_qir_trunc },

1323 [TGSI_OPCODE_CEIL] = { 0, tgsi_to_qir_ceil },

1324 [TGSI_OPCODE_FRC] = { 0, tgsi_to_qir_frc },

1325 [TGSI_OPCODE_FLR] = { 0, tgsi_to_qir_flr },

1326 [TGSI_OPCODE_SIN] = { 0, tgsi_to_qir_sin },

1327 [TGSI_OPCODE_COS] = { 0, tgsi_to_qir_cos },

1328 [TGSI_OPCODE_CLAMP] = { 0, tgsi_to_qir_clamp },

1329 [TGSI_OPCODE_SSG] = { 0, tgsi_to_qir_ssg },

1330 [TGSI_OPCODE_ARL] = { 0, tgsi_to_qir_arl },

1331 [TGSI_OPCODE_UARL] = { 0, tgsi_to_qir_uarl },

1332 };

1333 static int asdf = 0;

1334 uint32_t tgsi_op = tgsi_inst->Instruction.Opcode;

1335

1336 if (tgsi_op == TGSI_OPCODE_END)

1337 return;

1338

1339 struct qreg src_regs[12];

1340 for (int s = 0; s < 3; s++) {

1341 for (int i = 0; i < 4; i++) {

1342 src_regs[4 * s + i] =

1343 get_src(c, tgsi_inst->Instruction.Opcode,

1344 &tgsi_inst->Src[s], i);

1345 }

1346 }

1347

1348 switch (tgsi_op) {

1349 case TGSI_OPCODE_TEX:

1350 case TGSI_OPCODE_TXP:

1351 case TGSI_OPCODE_TXB:

1352 case TGSI_OPCODE_TXL:

1353 tgsi_to_qir_tex(c, tgsi_inst,

1354 op_trans[tgsi_op].op, src_regs);

1355 return;

1356 case TGSI_OPCODE_KILL:

1357 c->discard = qir_uniform_f(c, 1.0);

1358 return;

1359 case TGSI_OPCODE_KILL_IF:

1360 for (int i = 0; i < 4; i++)

1361 tgsi_to_qir_kill_if(c, src_regs, i);

1362 return;

1363 default:

1364 break;

1365 }

1366

1367 if (tgsi_op > ARRAY_SIZE(op_trans) || !(op_trans[tgsi_op].func)) {

1368 fprintf(stderr, "unknown tgsi inst: ");

1369 tgsi_dump_instruction(tgsi_inst, asdf++);

1370 fprintf(stderr, "\n");

1371 abort();

1372 }

1373

1374 for (int i = 0; i < 4; i++) {

1375 if (!(tgsi_inst->Dst[0].Register.WriteMask & (1 << i)))

1376 continue;

1377

1378 struct qreg result;

1379

1380 result = op_trans[tgsi_op].func(c, tgsi_inst,

1381 op_trans[tgsi_op].op,

1382 src_regs, i);

1383

1384 if (tgsi_inst->Instruction.Saturate) {

1385 float low = (tgsi_inst->Instruction.Saturate ==

1386 TGSI_SAT_MINUS_PLUS_ONE ? -1.0 : 0.0);

1387 result = qir_FMAX(c,

1388 qir_FMIN(c,

1389 result,

1390 qir_uniform_f(c, 1.0)),

1391 qir_uniform_f(c, low));

1392 }

1393

1394 update_dst(c, tgsi_inst, i, result);

1395 }

1396 }

1397

1398 static void

1399 parse_tgsi_immediate(struct vc4_compile *c, struct tgsi_full_immediate *imm)

1400 {

1401 for (int i = 0; i < 4; i++) {

1402 unsigned n = c->num_consts++;

1403 resize_qreg_array(c, &c->consts, &c->consts_array_size, n + 1);

1404 c->consts[n] = qir_uniform_ui(c, imm->u[i].Uint);

1405 }

1406 }

1407

1408 static struct qreg

1409 vc4_blend_channel(struct vc4_compile *c,

1410 struct qreg *dst,

1411 struct qreg *src,

1412 struct qreg val,

1413 unsigned factor,

1414 int channel)

1415 {

1416 switch(factor) {

1417 case PIPE_BLENDFACTOR_ONE:

1418 return val;

1419 case PIPE_BLENDFACTOR_SRC_COLOR:

1420 return qir_FMUL(c, val, src[channel]);

1421 case PIPE_BLENDFACTOR_SRC_ALPHA:

1422 return qir_FMUL(c, val, src[3]);

1423 case PIPE_BLENDFACTOR_DST_ALPHA:

1424 return qir_FMUL(c, val, dst[3]);

1425 case PIPE_BLENDFACTOR_DST_COLOR:

1426 return qir_FMUL(c, val, dst[channel]);

1427 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:

1428 if (channel != 3) {

1429 return qir_FMUL(c,

1430 val,

1431 qir_FMIN(c,

1432 src[3],

1433 qir_FSUB(c,

1434 qir_uniform_f(c, 1.0),

1435 dst[3])));

1436 } else {

1437 return val;

1438 }

1439 case PIPE_BLENDFACTOR_CONST_COLOR:

1440 return qir_FMUL(c, val,

1441 get_temp_for_uniform(c,

1442 QUNIFORM_BLEND_CONST_COLOR,

1443 channel));

1444 case PIPE_BLENDFACTOR_CONST_ALPHA:

1445 return qir_FMUL(c, val,

1446 get_temp_for_uniform(c,

1447 QUNIFORM_BLEND_CONST_COLOR,

1448 3));

1449 case PIPE_BLENDFACTOR_ZERO:

1450 return qir_uniform_f(c, 0.0);

1451 case PIPE_BLENDFACTOR_INV_SRC_COLOR:

1452 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),

1453 src[channel]));

1454 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:

1455 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),

1456 src[3]));

1457 case PIPE_BLENDFACTOR_INV_DST_ALPHA:

1458 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),

1459 dst[3]));

1460 case PIPE_BLENDFACTOR_INV_DST_COLOR:

1461 return qir_FMUL(c, val, qir_FSUB(c, qir_uniform_f(c, 1.0),

1462 dst[channel]));

1463 case PIPE_BLENDFACTOR_INV_CONST_COLOR:

1464 return qir_FMUL(c, val,

1465 qir_FSUB(c, qir_uniform_f(c, 1.0),

1466 get_temp_for_uniform(c,

1467 QUNIFORM_BLEND_CONST_COLOR,

1468 channel)));

1469 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:

1470 return qir_FMUL(c, val,

1471 qir_FSUB(c, qir_uniform_f(c, 1.0),

1472 get_temp_for_uniform(c,

1473 QUNIFORM_BLEND_CONST_COLOR,

1474 3)));

1475

1476 default:

1477 case PIPE_BLENDFACTOR_SRC1_COLOR:

1478 case PIPE_BLENDFACTOR_SRC1_ALPHA:

1479 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:

1480 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:

1481 /* Unsupported. */

1482 fprintf(stderr, "Unknown blend factor %d\n", factor);

1483 return val;

1484 }

1485 }

1486

1487 static struct qreg

1488 vc4_blend_func(struct vc4_compile *c,

1489 struct qreg src, struct qreg dst,

1490 unsigned func)

1491 {

1492 switch (func) {

1493 case PIPE_BLEND_ADD:

1494 return qir_FADD(c, src, dst);

1495 case PIPE_BLEND_SUBTRACT:

1496 return qir_FSUB(c, src, dst);

1497 case PIPE_BLEND_REVERSE_SUBTRACT:

1498 return qir_FSUB(c, dst, src);

1499 case PIPE_BLEND_MIN:

1500 return qir_FMIN(c, src, dst);

1501 case PIPE_BLEND_MAX:

1502 return qir_FMAX(c, src, dst);

1503

1504 default:

1505 /* Unsupported. */

1506 fprintf(stderr, "Unknown blend func %d\n", func);

1507 return src;

1508

1509 }

1510 }

1511

1512 /**

1513 * Implements fixed function blending in shader code.

1514 *

1515 * VC4 doesn't have any hardware support for blending. Instead, you read the

1516 * current contents of the destination from the tile buffer after having

1517 * waited for the scoreboard (which is handled by vc4_qpu_emit.c), then do

1518 * math using your output color and that destination value, and update the

1519 * output color appropriately.

1520 */

1521 static void

1522 vc4_blend(struct vc4_compile *c, struct qreg *result,

1523 struct qreg *dst_color, struct qreg *src_color)

1524 {

1525 struct pipe_rt_blend_state *blend = &c->fs_key->blend;

1526

1527 if (!blend->blend_enable) {

1528 for (int i = 0; i < 4; i++)

1529 result[i] = src_color[i];

1530 return;

1531 }

1532

1533 struct qreg src_blend[4], dst_blend[4];

1534 for (int i = 0; i < 3; i++) {

1535 src_blend[i] = vc4_blend_channel(c,

1536 dst_color, src_color,

1537 src_color[i],

1538 blend->rgb_src_factor, i);

1539 dst_blend[i] = vc4_blend_channel(c,

1540 dst_color, src_color,

1541 dst_color[i],

1542 blend->rgb_dst_factor, i);

1543 }

1544 src_blend[3] = vc4_blend_channel(c,

1545 dst_color, src_color,

1546 src_color[3],

1547 blend->alpha_src_factor, 3);

1548 dst_blend[3] = vc4_blend_channel(c,

1549 dst_color, src_color,

1550 dst_color[3],

1551 blend->alpha_dst_factor, 3);

1552

1553 for (int i = 0; i < 3; i++) {

1554 result[i] = vc4_blend_func(c,

1555 src_blend[i], dst_blend[i],

1556 blend->rgb_func);

1557 }

1558 result[3] = vc4_blend_func(c,

1559 src_blend[3], dst_blend[3],

1560 blend->alpha_func);

1561 }

1562

1563 static void

1564 clip_distance_discard(struct vc4_compile *c)

1565 {

1566 for (int i = 0; i < PIPE_MAX_CLIP_PLANES; i++) {

1567 if (!(c->key->ucp_enables & (1 << i)))

1568 continue;

1569

1570 struct qreg dist = emit_fragment_varying(c,

1571 TGSI_SEMANTIC_CLIPDIST,

1572 i,

1573 TGSI_SWIZZLE_X);

1574

1575 qir_SF(c, dist);

1576

1577 if (c->discard.file == QFILE_NULL)

1578 c->discard = qir_uniform_f(c, 0.0);

1579

1580 c->discard = qir_SEL_X_Y_NS(c, qir_uniform_f(c, 1.0),

1581 c->discard);

1582 }

1583 }

1584

1585 static void

1586 alpha_test_discard(struct vc4_compile *c)

1587 {

1588 struct qreg src_alpha;

1589 struct qreg alpha_ref = get_temp_for_uniform(c, QUNIFORM_ALPHA_REF, 0);

1590

1591 if (!c->fs_key->alpha_test)

1592 return;

1593

1594 if (c->output_color_index != -1)

1595 src_alpha = c->outputs[c->output_color_index + 3];

1596 else

1597 src_alpha = qir_uniform_f(c, 1.0);

1598

1599 if (c->discard.file == QFILE_NULL)

1600 c->discard = qir_uniform_f(c, 0.0);

1601

1602 switch (c->fs_key->alpha_test_func) {

1603 case PIPE_FUNC_NEVER:

1604 c->discard = qir_uniform_f(c, 1.0);

1605 break;

1606 case PIPE_FUNC_ALWAYS:

1607 break;

1608 case PIPE_FUNC_EQUAL:

1609 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));

1610 c->discard = qir_SEL_X_Y_ZS(c, c->discard,

1611 qir_uniform_f(c, 1.0));

1612 break;

1613 case PIPE_FUNC_NOTEQUAL:

1614 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));

1615 c->discard = qir_SEL_X_Y_ZC(c, c->discard,

1616 qir_uniform_f(c, 1.0));

1617 break;

1618 case PIPE_FUNC_GREATER:

1619 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));

1620 c->discard = qir_SEL_X_Y_NC(c, c->discard,

1621 qir_uniform_f(c, 1.0));

1622 break;

1623 case PIPE_FUNC_GEQUAL:

1624 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));

1625 c->discard = qir_SEL_X_Y_NS(c, c->discard,

1626 qir_uniform_f(c, 1.0));

1627 break;

1628 case PIPE_FUNC_LESS:

1629 qir_SF(c, qir_FSUB(c, src_alpha, alpha_ref));

1630 c->discard = qir_SEL_X_Y_NS(c, c->discard,

1631 qir_uniform_f(c, 1.0));

1632 break;

1633 case PIPE_FUNC_LEQUAL:

1634 qir_SF(c, qir_FSUB(c, alpha_ref, src_alpha));

1635 c->discard = qir_SEL_X_Y_NC(c, c->discard,

1636 qir_uniform_f(c, 1.0));

1637 break;

1638 }

1639 }

1640

1641 static struct qreg

1642 vc4_logicop(struct vc4_compile *c, struct qreg src, struct qreg dst)

1643 {

1644 switch (c->fs_key->logicop_func) {

1645 case PIPE_LOGICOP_CLEAR:

1646 return qir_uniform_f(c, 0.0);

1647 case PIPE_LOGICOP_NOR:

1648 return qir_NOT(c, qir_OR(c, src, dst));

1649 case PIPE_LOGICOP_AND_INVERTED:

1650 return qir_AND(c, qir_NOT(c, src), dst);

1651 case PIPE_LOGICOP_COPY_INVERTED:

1652 return qir_NOT(c, src);

1653 case PIPE_LOGICOP_AND_REVERSE:

1654 return qir_AND(c, src, qir_NOT(c, dst));

1655 case PIPE_LOGICOP_INVERT:

1656 return qir_NOT(c, dst);

1657 case PIPE_LOGICOP_XOR:

1658 return qir_XOR(c, src, dst);

1659 case PIPE_LOGICOP_NAND:

1660 return qir_NOT(c, qir_AND(c, src, dst));

1661 case PIPE_LOGICOP_AND:

1662 return qir_AND(c, src, dst);

1663 case PIPE_LOGICOP_EQUIV:

1664 return qir_NOT(c, qir_XOR(c, src, dst));

1665 case PIPE_LOGICOP_NOOP:

1666 return dst;

1667 case PIPE_LOGICOP_OR_INVERTED:

1668 return qir_OR(c, qir_NOT(c, src), dst);

1669 case PIPE_LOGICOP_OR_REVERSE:

1670 return qir_OR(c, src, qir_NOT(c, dst));

1671 case PIPE_LOGICOP_OR:

1672 return qir_OR(c, src, dst);

1673 case PIPE_LOGICOP_SET:

1674 return qir_uniform_ui(c, ~0);

1675 case PIPE_LOGICOP_COPY:

1676 default:

1677 return src;

1678 }

1679 }

1680

1681 static void

1682 emit_frag_end(struct vc4_compile *c)

1683 {

1684 clip_distance_discard(c);

1685 alpha_test_discard(c);

1686

1687 enum pipe_format color_format = c->fs_key->color_format;

1688 const uint8_t *format_swiz = vc4_get_format_swizzle(color_format);

1689 struct qreg tlb_read_color[4] = { c->undef, c->undef, c->undef, c->undef };

1690 struct qreg dst_color[4] = { c->undef, c->undef, c->undef, c->undef };

1691 struct qreg linear_dst_color[4] = { c->undef, c->undef, c->undef, c->undef };

1692 struct qreg packed_dst_color = c->undef;

1693

1694 if (c->fs_key->blend.blend_enable ||

1695 c->fs_key->blend.colormask != 0xf ||

1696 c->fs_key->logicop_func != PIPE_LOGICOP_COPY) {

1697 struct qreg r4 = qir_TLB_COLOR_READ(c);

1698 for (int i = 0; i < 4; i++)

1699 tlb_read_color[i] = qir_R4_UNPACK(c, r4, i);

1700 for (int i = 0; i < 4; i++) {

1701 dst_color[i] = get_swizzled_channel(c,

1702 tlb_read_color,

1703 format_swiz[i]);

1704 if (util_format_is_srgb(color_format) && i != 3) {

1705 linear_dst_color[i] =

1706 qir_srgb_decode(c, dst_color[i]);

1707 } else {

1708 linear_dst_color[i] = dst_color[i];

1709 }

1710 }

1711

1712 /* Save the packed value for logic ops. Can't reuse r4

1713 * becuase other things might smash it (like sRGB)

1714 */

1715 packed_dst_color = qir_MOV(c, r4);

1716 }

1717

1718 struct qreg blend_color[4];

1719 struct qreg undef_array[4] = {

1720 c->undef, c->undef, c->undef, c->undef

1721 };

1722 vc4_blend(c, blend_color, linear_dst_color,

1723 (c->output_color_index != -1 ?

1724 c->outputs + c->output_color_index :

1725 undef_array));

1726

1727 if (util_format_is_srgb(color_format)) {

1728 for (int i = 0; i < 3; i++)

1729 blend_color[i] = qir_srgb_encode(c, blend_color[i]);

1730 }

1731

1732 /* If the bit isn't set in the color mask, then just return the

1733 * original dst color, instead.

1734 */

1735 for (int i = 0; i < 4; i++) {

1736 if (!(c->fs_key->blend.colormask & (1 << i))) {

1737 blend_color[i] = dst_color[i];

1738 }

1739 }

1740

1741 /* Debug: Sometimes you're getting a black output and just want to see

1742 * if the FS is getting executed at all. Spam magenta into the color

1743 * output.

1744 */

1745 if (0) {

1746 blend_color[0] = qir_uniform_f(c, 1.0);

1747 blend_color[1] = qir_uniform_f(c, 0.0);

1748 blend_color[2] = qir_uniform_f(c, 1.0);

1749 blend_color[3] = qir_uniform_f(c, 0.5);

1750 }

1751

1752 struct qreg swizzled_outputs[4];

1753 for (int i = 0; i < 4; i++) {

1754 swizzled_outputs[i] = get_swizzled_channel(c, blend_color,

1755 format_swiz[i]);

1756 }

1757

1758 if (c->discard.file != QFILE_NULL)

1759 qir_TLB_DISCARD_SETUP(c, c->discard);

1760

1761 if (c->fs_key->stencil_enabled) {

1762 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 0));

1763 if (c->fs_key->stencil_twoside) {

1764 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 1));

1765 }

1766 if (c->fs_key->stencil_full_writemasks) {

1767 qir_TLB_STENCIL_SETUP(c, add_uniform(c, QUNIFORM_STENCIL, 2));

1768 }

1769 }

1770

1771 if (c->fs_key->depth_enabled) {

1772 struct qreg z;

1773 if (c->output_position_index != -1) {

1774 z = qir_FTOI(c, qir_FMUL(c, c->outputs[c->output_position_index + 2],

1775 qir_uniform_f(c, 0xffffff)));

1776 } else {

1777 z = qir_FRAG_Z(c);

1778 }

1779 qir_TLB_Z_WRITE(c, z);

1780 }

1781

1782 bool color_written = false;

1783 for (int i = 0; i < 4; i++) {

1784 if (swizzled_outputs[i].file != QFILE_NULL)

1785 color_written = true;

1786 }

1787

1788 struct qreg packed_color;

1789 if (color_written) {

1790 /* Fill in any undefined colors. The simulator will assertion

1791 * fail if we read something that wasn't written, and I don't

1792 * know what hardware does.

1793 */

1794 for (int i = 0; i < 4; i++) {

1795 if (swizzled_outputs[i].file == QFILE_NULL)

1796 swizzled_outputs[i] = qir_uniform_f(c, 0.0);

1797 }

1798 packed_color = qir_get_temp(c);

1799 qir_emit(c, qir_inst4(QOP_PACK_COLORS, packed_color,

1800 swizzled_outputs[0],

1801 swizzled_outputs[1],

1802 swizzled_outputs[2],

1803 swizzled_outputs[3]));

1804 } else {

1805 packed_color = qir_uniform_ui(c, 0);

1806 }

1807

1808

1809 if (c->fs_key->logicop_func != PIPE_LOGICOP_COPY) {

1810 packed_color = vc4_logicop(c, packed_color, packed_dst_color);

1811 }

1812

1813 qir_emit(c, qir_inst(QOP_TLB_COLOR_WRITE, c->undef,

1814 packed_color, c->undef));

1815 }

1816

1817 static void

1818 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)

1819 {

1820 struct qreg xyi[2];

1821

1822 for (int i = 0; i < 2; i++) {

1823 struct qreg scale =

1824 add_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);

1825

1826 xyi[i] = qir_FTOI(c, qir_FMUL(c,

1827 qir_FMUL(c,

1828 c->outputs[c->output_position_index + i],

1829 scale),

1830 rcp_w));

1831 }

1832

1833 qir_VPM_WRITE(c, qir_PACK_SCALED(c, xyi[0], xyi[1]));

1834 }

1835

1836 static void

1837 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)

1838 {

1839 struct qreg zscale = add_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);

1840 struct qreg zoffset = add_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);

1841

1842 qir_VPM_WRITE(c, qir_FMUL(c, qir_FADD(c, qir_FMUL(c,

1843 c->outputs[c->output_position_index + 2],

1844 zscale),

1845 zoffset),

1846 rcp_w));

1847 }

1848

1849 static void

1850 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)

1851 {

1852 qir_VPM_WRITE(c, rcp_w);

1853 }

1854

1855 static void

1856 emit_point_size_write(struct vc4_compile *c)

1857 {

1858 struct qreg point_size;

1859

1860 if (c->output_point_size_index)

1861 point_size = c->outputs[c->output_point_size_index + 3];

1862 else

1863 point_size = qir_uniform_f(c, 1.0);

1864

1865 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,

1866 * BCM21553).

1867 */

1868 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));

1869

1870 qir_VPM_WRITE(c, point_size);

1871 }

1872

1873 /**

1874 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.

1875 *

1876 * The simulator insists that there be at least one vertex attribute, so

1877 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also

1878 * insists that all vertex attributes loaded get read by the VS/CS, so we have

1879 * to consume it here.

1880 */

1881 static void

1882 emit_stub_vpm_read(struct vc4_compile *c)

1883 {

1884 if (c->num_inputs)

1885 return;

1886

1887 for (int i = 0; i < 4; i++) {

1888 qir_emit(c, qir_inst(QOP_VPM_READ,

1889 qir_get_temp(c),

1890 c->undef,

1891 c->undef));

1892 c->num_inputs++;

1893 }

1894 }

1895

1896 static void

1897 emit_ucp_clipdistance(struct vc4_compile *c)

1898 {

1899 unsigned cv;

1900 if (c->output_clipvertex_index != -1)

1901 cv = c->output_clipvertex_index;

1902 else if (c->output_position_index != -1)

1903 cv = c->output_position_index;

1904 else

1905 return;

1906

1907 for (int plane = 0; plane < PIPE_MAX_CLIP_PLANES; plane++) {

1908 if (!(c->key->ucp_enables & (1 << plane)))

1909 continue;

1910

1911 /* Pick the next outputs[] that hasn't been written to, since

1912 * there are no other program writes left to be processed at

1913 * this point. If something had been declared but not written

1914 * (like a w component), we'll just smash over the top of it.

1915 */

1916 uint32_t output_index = c->num_outputs++;

1917 add_output(c, output_index,

1918 TGSI_SEMANTIC_CLIPDIST,

1919 plane,

1920 TGSI_SWIZZLE_X);

1921

1922

1923 struct qreg dist = qir_uniform_f(c, 0.0);

1924 for (int i = 0; i < 4; i++) {

1925 struct qreg pos_chan = c->outputs[cv + i];

1926 struct qreg ucp =

1927 add_uniform(c, QUNIFORM_USER_CLIP_PLANE,

1928 plane * 4 + i);

1929 dist = qir_FADD(c, dist, qir_FMUL(c, pos_chan, ucp));

1930 }

1931

1932 c->outputs[output_index] = dist;

1933 }

1934 }

1935

1936 static void

1937 emit_vert_end(struct vc4_compile *c,

1938 struct vc4_varying_semantic *fs_inputs,

1939 uint32_t num_fs_inputs)

1940 {

1941 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);

1942

1943 emit_stub_vpm_read(c);

1944 emit_ucp_clipdistance(c);

1945

1946 emit_scaled_viewport_write(c, rcp_w);

1947 emit_zs_write(c, rcp_w);

1948 emit_rcp_wc_write(c, rcp_w);

1949 if (c->vs_key->per_vertex_point_size)

1950 emit_point_size_write(c);

1951

1952 for (int i = 0; i < num_fs_inputs; i++) {

1953 struct vc4_varying_semantic *input = &fs_inputs[i];

1954 int j;

1955

1956 for (j = 0; j < c->num_outputs; j++) {

1957 struct vc4_varying_semantic *output =

1958 &c->output_semantics[j];

1959

1960 if (input->semantic == output->semantic &&

1961 input->index == output->index &&

1962 input->swizzle == output->swizzle) {

1963 qir_VPM_WRITE(c, c->outputs[j]);

1964 break;

1965 }

1966 }

1967 /* Emit padding if we didn't find a declared VS output for

1968 * this FS input.

1969 */

1970 if (j == c->num_outputs)

1971 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));

1972 }

1973 }

1974

1975 static void

1976 emit_coord_end(struct vc4_compile *c)

1977 {

1978 struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 3]);

1979

1980 emit_stub_vpm_read(c);

1981

1982 for (int i = 0; i < 4; i++)

1983 qir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);

1984

1985 emit_scaled_viewport_write(c, rcp_w);

1986 emit_zs_write(c, rcp_w);

1987 emit_rcp_wc_write(c, rcp_w);

1988 if (c->vs_key->per_vertex_point_size)

1989 emit_point_size_write(c);

1990 }

1991

1992 static struct vc4_compile *

1993 vc4_shader_tgsi_to_qir(struct vc4_context *vc4, enum qstage stage,

1994 struct vc4_key *key)

1995 {

1996 struct vc4_compile *c = qir_compile_init();

1997 int ret;

1998

1999 c->stage = stage;

2000 for (int i = 0; i < 4; i++)

2001 c->addr[i] = qir_uniform_f(c, 0.0);

2002

2003 c->shader_state = &key->shader_state->base;

2004 c->program_id = key->shader_state->program_id;

2005 c->variant_id = key->shader_state->compiled_variant_count++;

2006

2007 c->key = key;

2008 switch (stage) {

2009 case QSTAGE_FRAG:

2010 c->fs_key = (struct vc4_fs_key *)key;

2011 if (c->fs_key->is_points) {

2012 c->point_x = emit_fragment_varying(c, ~0, ~0, 0);

2013 c->point_y = emit_fragment_varying(c, ~0, ~0, 0);

2014 } else if (c->fs_key->is_lines) {

2015 c->line_x = emit_fragment_varying(c, ~0, ~0, 0);

2016 }

2017 break;

2018 case QSTAGE_VERT:

2019 c->vs_key = (struct vc4_vs_key *)key;

2020 break;

2021 case QSTAGE_COORD:

2022 c->vs_key = (struct vc4_vs_key *)key;

2023 break;

2024 }

2025

2026 const struct tgsi_token *tokens = key->shader_state->base.tokens;

2027 if (c->fs_key && c->fs_key->light_twoside) {

2028 if (!key->shader_state->twoside_tokens) {

2029 const struct tgsi_lowering_config lowering_config = {

2030 .color_two_side = true,

2031 };

2032 struct tgsi_shader_info info;

2033 key->shader_state->twoside_tokens =

2034 tgsi_transform_lowering(&lowering_config,

2035 key->shader_state->base.tokens,

2036 &info);

2037

2038 /* If no transformation occurred, then NULL is

2039 * returned and we just use our original tokens.

2040 */

2041 if (!key->shader_state->twoside_tokens) {

2042 key->shader_state->twoside_tokens =

2043 key->shader_state->base.tokens;

2044 }

2045 }

2046 tokens = key->shader_state->twoside_tokens;

2047 }

2048

2049 ret = tgsi_parse_init(&c->parser, tokens);

2050 assert(ret == TGSI_PARSE_OK);

2051

2052 if (vc4_debug & VC4_DEBUG_TGSI) {

2053 fprintf(stderr, "%s prog %d/%d TGSI:\n",

2054 qir_get_stage_name(c->stage),

2055 c->program_id, c->variant_id);

2056 tgsi_dump(tokens, 0);

2057 }

2058

2059 while (!tgsi_parse_end_of_tokens(&c->parser)) {

2060 tgsi_parse_token(&c->parser);

2061

2062 switch (c->parser.FullToken.Token.Type) {

2063 case TGSI_TOKEN_TYPE_DECLARATION:

2064 emit_tgsi_declaration(c,

2065 &c->parser.FullToken.FullDeclaration);

2066 break;

2067

2068 case TGSI_TOKEN_TYPE_INSTRUCTION:

2069 emit_tgsi_instruction(c,

2070 &c->parser.FullToken.FullInstruction);

2071 break;

2072

2073 case TGSI_TOKEN_TYPE_IMMEDIATE:

2074 parse_tgsi_immediate(c,

2075 &c->parser.FullToken.FullImmediate);

2076 break;

2077 }

2078 }

2079

2080 switch (stage) {

2081 case QSTAGE_FRAG:

2082 emit_frag_end(c);

2083 break;

2084 case QSTAGE_VERT:

2085 emit_vert_end(c,

2086 vc4->prog.fs->input_semantics,

2087 vc4->prog.fs->num_inputs);

2088 break;

2089 case QSTAGE_COORD:

2090 emit_coord_end(c);

2091 break;

2092 }

2093

2094 tgsi_parse_free(&c->parser);

2095

2096 qir_optimize(c);

2097

2098 if (vc4_debug & VC4_DEBUG_QIR) {

2099 fprintf(stderr, "%s prog %d/%d QIR:\n",

2100 qir_get_stage_name(c->stage),

2101 c->program_id, c->variant_id);

2102 qir_dump(c);

2103 }

2104 qir_reorder_uniforms(c);

2105 vc4_generate_code(vc4, c);

2106

2107 if (vc4_debug & VC4_DEBUG_SHADERDB) {

2108 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d instructions\n",

2109 qir_get_stage_name(c->stage),

2110 c->program_id, c->variant_id,

2111 c->qpu_inst_count);

2112 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d uniforms\n",

2113 qir_get_stage_name(c->stage),

2114 c->program_id, c->variant_id,

2115 c->num_uniforms);

2116 }

2117

2118 return c;

2119 }

2120

2121 static void *

2122 vc4_shader_state_create(struct pipe_context *pctx,

2123 const struct pipe_shader_state *cso)

2124 {

2125 struct vc4_context *vc4 = vc4_context(pctx);

2126 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);

2127 if (!so)

2128 return NULL;

2129

2130 const struct tgsi_lowering_config lowering_config = {

2131 .lower_DST = true,

2132 .lower_XPD = true,

2133 .lower_SCS = true,

2134 .lower_POW = true,

2135 .lower_LIT = true,

2136 .lower_EXP = true,

2137 .lower_LOG = true,

2138 .lower_DP4 = true,

2139 .lower_DP3 = true,

2140 .lower_DPH = true,

2141 .lower_DP2 = true,

2142 .lower_DP2A = true,

2143 };

2144

2145 struct tgsi_shader_info info;

2146 so->base.tokens = tgsi_transform_lowering(&lowering_config, cso->tokens, &info);

2147 if (!so->base.tokens)

2148 so->base.tokens = tgsi_dup_tokens(cso->tokens);

2149 so->program_id = vc4->next_uncompiled_program_id++;

2150

2151 return so;

2152 }

2153

2154 static void

2155 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,

2156 struct vc4_compile *c)

2157 {

2158 int count = c->num_uniforms;

2159 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;

2160

2161 uinfo->count = count;

2162 uinfo->data = ralloc_array(shader, uint32_t, count);

2163 memcpy(uinfo->data, c->uniform_data,

2164 count * sizeof(*uinfo->data));

2165 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);

2166 memcpy(uinfo->contents, c->uniform_contents,

2167 count * sizeof(*uinfo->contents));

2168 uinfo->num_texture_samples = c->num_texture_samples;

2169 }

2170

2171 static struct vc4_compiled_shader *

2172 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,

2173 struct vc4_key *key)

2174 {

2175 struct hash_table *ht;

2176 uint32_t key_size;

2177 if (stage == QSTAGE_FRAG) {

2178 ht = vc4->fs_cache;

2179 key_size = sizeof(struct vc4_fs_key);

2180 } else {

2181 ht = vc4->vs_cache;

2182 key_size = sizeof(struct vc4_vs_key);

2183 }

2184

2185 struct vc4_compiled_shader *shader;

2186 struct hash_entry *entry = _mesa_hash_table_search(ht, key);

2187 if (entry)

2188 return entry->data;

2189

2190 struct vc4_compile *c = vc4_shader_tgsi_to_qir(vc4, stage, key);

2191 shader = rzalloc(NULL, struct vc4_compiled_shader);

2192

2193 shader->program_id = vc4->next_compiled_program_id++;

2194 if (stage == QSTAGE_FRAG) {

2195 bool input_live[c->num_input_semantics];

2196 struct simple_node *node;

2197

2198 memset(input_live, 0, sizeof(input_live));

2199 foreach(node, &c->instructions) {

2200 struct qinst *inst = (struct qinst *)node;

2201 for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {

2202 if (inst->src[i].file == QFILE_VARY)

2203 input_live[inst->src[i].index] = true;

2204 }

2205 }

2206

2207 shader->input_semantics = ralloc_array(shader,

2208 struct vc4_varying_semantic,

2209 c->num_input_semantics);

2210

2211 for (int i = 0; i < c->num_input_semantics; i++) {

2212 struct vc4_varying_semantic *sem = &c->input_semantics[i];

2213

2214 if (!input_live[i])

2215 continue;

2216

2217 /* Skip non-VS-output inputs. */

2218 if (sem->semantic == (uint8_t)~0)

2219 continue;

2220

2221 if (sem->semantic == TGSI_SEMANTIC_COLOR ||

2222 sem->semantic == TGSI_SEMANTIC_BCOLOR) {

2223 shader->color_inputs |= (1 << shader->num_inputs);

2224 }

2225

2226 shader->input_semantics[shader->num_inputs] = *sem;

2227 shader->num_inputs++;

2228 }

2229 } else {

2230 shader->num_inputs = c->num_inputs;

2231 }

2232

2233 copy_uniform_state_to_shader(shader, c);

2234 shader->bo = vc4_bo_alloc_mem(vc4->screen, c->qpu_insts,

2235 c->qpu_inst_count * sizeof(uint64_t),

2236 "code");

2237

2238 /* Copy the compiler UBO range state to the compiled shader, dropping

2239 * out arrays that were never referenced by an indirect load.

2240 *

2241 * (Note that QIR dead code elimination of an array access still

2242 * leaves that array alive, though)

2243 */

2244 if (c->num_ubo_ranges) {

2245 shader->num_ubo_ranges = c->num_ubo_ranges;

2246 shader->ubo_ranges = ralloc_array(shader, struct vc4_ubo_range,

2247 c->num_ubo_ranges);

2248 uint32_t j = 0;

2249 for (int i = 0; i < c->ubo_ranges_array_size; i++) {

2250 struct vc4_compiler_ubo_range *range =

2251 &c->ubo_ranges[i];

2252 if (!range->used)

2253 continue;

2254

2255 shader->ubo_ranges[j].dst_offset = range->dst_offset;

2256 shader->ubo_ranges[j].src_offset = range->src_offset;

2257 shader->ubo_ranges[j].size = range->size;

2258 shader->ubo_size += c->ubo_ranges[i].size;

2259 j++;

2260 }

2261 }

2262

2263 qir_compile_destroy(c);

2264

2265 struct vc4_key *dup_key;

2266 dup_key = ralloc_size(shader, key_size);

2267 memcpy(dup_key, key, key_size);

2268 _mesa_hash_table_insert(ht, dup_key, shader);

2269

2270 return shader;

2271 }

2272

2273 static void

2274 vc4_setup_shared_key(struct vc4_context *vc4, struct vc4_key *key,

2275 struct vc4_texture_stateobj *texstate)

2276 {

2277 for (int i = 0; i < texstate->num_textures; i++) {

2278 struct pipe_sampler_view *sampler = texstate->textures[i];

2279 struct pipe_sampler_state *sampler_state =

2280 texstate->samplers[i];

2281

2282 if (sampler) {

2283 key->tex[i].format = sampler->format;

2284 key->tex[i].swizzle[0] = sampler->swizzle_r;

2285 key->tex[i].swizzle[1] = sampler->swizzle_g;

2286 key->tex[i].swizzle[2] = sampler->swizzle_b;

2287 key->tex[i].swizzle[3] = sampler->swizzle_a;

2288 key->tex[i].compare_mode = sampler_state->compare_mode;

2289 key->tex[i].compare_func = sampler_state->compare_func;

2290 key->tex[i].wrap_s = sampler_state->wrap_s;

2291 key->tex[i].wrap_t = sampler_state->wrap_t;

2292 }

2293 }

2294

2295 key->ucp_enables = vc4->rasterizer->base.clip_plane_enable;

2296 }

2297

2298 static void

2299 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)

2300 {

2301 struct vc4_fs_key local_key;

2302 struct vc4_fs_key *key = &local_key;

2303

2304 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |

2305 VC4_DIRTY_BLEND |

2306 VC4_DIRTY_FRAMEBUFFER |

2307 VC4_DIRTY_ZSA |

2308 VC4_DIRTY_RASTERIZER |

2309 VC4_DIRTY_FRAGTEX |

2310 VC4_DIRTY_TEXSTATE |

2311 VC4_DIRTY_PROG))) {

2312 return;

2313 }

2314

2315 memset(key, 0, sizeof(*key));

2316 vc4_setup_shared_key(vc4, &key->base, &vc4->fragtex);

2317 key->base.shader_state = vc4->prog.bind_fs;

2318 key->is_points = (prim_mode == PIPE_PRIM_POINTS);

2319 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&

2320 prim_mode <= PIPE_PRIM_LINE_STRIP);

2321 key->blend = vc4->blend->rt[0];

2322 if (vc4->blend->logicop_enable) {

2323 key->logicop_func = vc4->blend->logicop_func;

2324 } else {

2325 key->logicop_func = PIPE_LOGICOP_COPY;

2326 }

2327 if (vc4->framebuffer.cbufs[0])

2328 key->color_format = vc4->framebuffer.cbufs[0]->format;

2329

2330 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;

2331 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;

2332 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;

2333 key->depth_enabled = (vc4->zsa->base.depth.enabled ||

2334 key->stencil_enabled);

2335 if (vc4->zsa->base.alpha.enabled) {

2336 key->alpha_test = true;

2337 key->alpha_test_func = vc4->zsa->base.alpha.func;

2338 }

2339

2340 if (key->is_points) {

2341 key->point_sprite_mask =

2342 vc4->rasterizer->base.sprite_coord_enable;

2343 key->point_coord_upper_left =

2344 (vc4->rasterizer->base.sprite_coord_mode ==

2345 PIPE_SPRITE_COORD_UPPER_LEFT);

2346 }

2347

2348 key->light_twoside = vc4->rasterizer->base.light_twoside;

2349

2350 struct vc4_compiled_shader *old_fs = vc4->prog.fs;

2351 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);

2352 if (vc4->prog.fs == old_fs)

2353 return;

2354

2355 if (vc4->rasterizer->base.flatshade &&

2356 old_fs && vc4->prog.fs->color_inputs != old_fs->color_inputs) {

2357 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;

2358 }

2359 }

2360

2361 static void

2362 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)

2363 {

2364 struct vc4_vs_key local_key;

2365 struct vc4_vs_key *key = &local_key;

2366

2367 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |

2368 VC4_DIRTY_RASTERIZER |

2369 VC4_DIRTY_VERTTEX |

2370 VC4_DIRTY_TEXSTATE |

2371 VC4_DIRTY_VTXSTATE |

2372 VC4_DIRTY_PROG))) {

2373 return;

2374 }

2375

2376 memset(key, 0, sizeof(*key));

2377 vc4_setup_shared_key(vc4, &key->base, &vc4->verttex);

2378 key->base.shader_state = vc4->prog.bind_vs;

2379 key->compiled_fs_id = vc4->prog.fs->program_id;

2380

2381 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)

2382 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;

2383

2384 key->per_vertex_point_size =

2385 (prim_mode == PIPE_PRIM_POINTS &&

2386 vc4->rasterizer->base.point_size_per_vertex);

2387

2388 vc4->prog.vs = vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);

2389 key->is_coord = true;

2390 vc4->prog.cs = vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);

2391 }

2392

2393 void

2394 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)

2395 {

2396 vc4_update_compiled_fs(vc4, prim_mode);

2397 vc4_update_compiled_vs(vc4, prim_mode);

2398 }

2399

2400 static uint32_t

2401 fs_cache_hash(const void *key)

2402 {

2403 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));

2404 }

2405

2406 static uint32_t

2407 vs_cache_hash(const void *key)

2408 {

2409 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));

2410 }

2411

2412 static bool

2413 fs_cache_compare(const void *key1, const void *key2)

2414 {

2415 return memcmp(key1, key2, sizeof(struct vc4_fs_key)) == 0;

2416 }

2417

2418 static bool

2419 vs_cache_compare(const void *key1, const void *key2)

2420 {

2421 return memcmp(key1, key2, sizeof(struct vc4_vs_key)) == 0;

2422 }

2423

2424 static void

2425 delete_from_cache_if_matches(struct hash_table *ht,

2426 struct hash_entry *entry,

2427 struct vc4_uncompiled_shader *so)

2428 {

2429 struct vc4_key *key = entry->data;

2430

2431 if (key->shader_state == so) {

2432 struct vc4_compiled_shader *shader = entry->data;

2433 _mesa_hash_table_remove(ht, entry);

2434 vc4_bo_unreference(&shader->bo);

2435 ralloc_free(shader);

2436 }

2437 }

2438

2439 static void

2440 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)

2441 {

2442 struct vc4_context *vc4 = vc4_context(pctx);

2443 struct vc4_uncompiled_shader *so = hwcso;

2444

2445 struct hash_entry *entry;

2446 hash_table_foreach(vc4->fs_cache, entry)

2447 delete_from_cache_if_matches(vc4->fs_cache, entry, so);

2448 hash_table_foreach(vc4->vs_cache, entry)

2449 delete_from_cache_if_matches(vc4->vs_cache, entry, so);

2450

2451 if (so->twoside_tokens != so->base.tokens)

2452 free((void *)so->twoside_tokens);

2453 free((void *)so->base.tokens);

2454 free(so);

2455 }

2456

2457 static uint32_t translate_wrap(uint32_t p_wrap, bool using_nearest)

2458 {

2459 switch (p_wrap) {

2460 case PIPE_TEX_WRAP_REPEAT:

2461 return 0;

2462 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:

2463 return 1;

2464 case PIPE_TEX_WRAP_MIRROR_REPEAT:

2465 return 2;

2466 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:

2467 return 3;

2468 case PIPE_TEX_WRAP_CLAMP:

2469 return (using_nearest ? 1 : 3);

2470 default:

2471 fprintf(stderr, "Unknown wrap mode %d\n", p_wrap);

2472 assert(!"not reached");

2473 return 0;

2474 }

2475 }

2476

2477 static void

2478 write_texture_p0(struct vc4_context *vc4,

2479 struct vc4_texture_stateobj *texstate,

2480 uint32_t unit)

2481 {

2482 struct pipe_sampler_view *texture = texstate->textures[unit];

2483 struct vc4_resource *rsc = vc4_resource(texture->texture);

2484

2485 cl_reloc(vc4, &vc4->uniforms, rsc->bo,

2486 VC4_SET_FIELD(rsc->slices[0].offset >> 12, VC4_TEX_P0_OFFSET) |

2487 VC4_SET_FIELD(texture->u.tex.last_level -

2488 texture->u.tex.first_level, VC4_TEX_P0_MIPLVLS) |

2489 VC4_SET_FIELD(texture->target == PIPE_TEXTURE_CUBE,

2490 VC4_TEX_P0_CMMODE) |

2491 VC4_SET_FIELD(rsc->vc4_format & 7, VC4_TEX_P0_TYPE));

2492 }

2493

2494 static void

2495 write_texture_p1(struct vc4_context *vc4,

2496 struct vc4_texture_stateobj *texstate,

2497 uint32_t unit)

2498 {

2499 struct pipe_sampler_view *texture = texstate->textures[unit];

2500 struct vc4_resource *rsc = vc4_resource(texture->texture);

2501 struct pipe_sampler_state *sampler = texstate->samplers[unit];

2502 static const uint8_t minfilter_map[6] = {

2503 VC4_TEX_P1_MINFILT_NEAR_MIP_NEAR,

2504 VC4_TEX_P1_MINFILT_LIN_MIP_NEAR,

2505 VC4_TEX_P1_MINFILT_NEAR_MIP_LIN,

2506 VC4_TEX_P1_MINFILT_LIN_MIP_LIN,

2507 VC4_TEX_P1_MINFILT_NEAREST,

2508 VC4_TEX_P1_MINFILT_LINEAR,

2509 };

2510 static const uint32_t magfilter_map[] = {

2511 [PIPE_TEX_FILTER_NEAREST] = VC4_TEX_P1_MAGFILT_NEAREST,

2512 [PIPE_TEX_FILTER_LINEAR] = VC4_TEX_P1_MAGFILT_LINEAR,

2513 };

2514

2515 bool either_nearest =

2516 (sampler->mag_img_filter == PIPE_TEX_MIPFILTER_NEAREST ||

2517 sampler->min_img_filter == PIPE_TEX_MIPFILTER_NEAREST);

2518

2519 cl_u32(&vc4->uniforms,

2520 VC4_SET_FIELD(rsc->vc4_format >> 4, VC4_TEX_P1_TYPE4) |

2521 VC4_SET_FIELD(texture->texture->height0 & 2047,

2522 VC4_TEX_P1_HEIGHT) |

2523 VC4_SET_FIELD(texture->texture->width0 & 2047,

2524 VC4_TEX_P1_WIDTH) |

2525 VC4_SET_FIELD(magfilter_map[sampler->mag_img_filter],

2526 VC4_TEX_P1_MAGFILT) |

2527 VC4_SET_FIELD(minfilter_map[sampler->min_mip_filter * 2 +

2528 sampler->min_img_filter],

2529 VC4_TEX_P1_MINFILT) |

2530 VC4_SET_FIELD(translate_wrap(sampler->wrap_s, either_nearest),

2531 VC4_TEX_P1_WRAP_S) |

2532 VC4_SET_FIELD(translate_wrap(sampler->wrap_t, either_nearest),

2533 VC4_TEX_P1_WRAP_T));

2534 }

2535

2536 static void

2537 write_texture_p2(struct vc4_context *vc4,

2538 struct vc4_texture_stateobj *texstate,

2539 uint32_t data)

2540 {

2541 uint32_t unit = data & 0xffff;

2542 struct pipe_sampler_view *texture = texstate->textures[unit];

2543 struct vc4_resource *rsc = vc4_resource(texture->texture);

2544

2545 cl_u32(&vc4->uniforms,

2546 VC4_SET_FIELD(VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE,

2547 VC4_TEX_P2_PTYPE) |

2548 VC4_SET_FIELD(rsc->cube_map_stride >> 12, VC4_TEX_P2_CMST) |

2549 VC4_SET_FIELD((data >> 16) & 1, VC4_TEX_P2_BSLOD));

2550 }

2551

2552

2553 #define SWIZ(x,y,z,w) { \

2554 UTIL_FORMAT_SWIZZLE_##x, \

2555 UTIL_FORMAT_SWIZZLE_##y, \

2556 UTIL_FORMAT_SWIZZLE_##z, \

2557 UTIL_FORMAT_SWIZZLE_##w \

2558 }

2559

2560 static void

2561 write_texture_border_color(struct vc4_context *vc4,

2562 struct vc4_texture_stateobj *texstate,

2563 uint32_t unit)

2564 {

2565 struct pipe_sampler_state *sampler = texstate->samplers[unit];

2566 struct pipe_sampler_view *texture = texstate->textures[unit];

2567 struct vc4_resource *rsc = vc4_resource(texture->texture);

2568 union util_color uc;

2569

2570 const struct util_format_description *tex_format_desc =

2571 util_format_description(texture->format);

2572

2573 float border_color[4];

2574 for (int i = 0; i < 4; i++)

2575 border_color[i] = sampler->border_color.f[i];

2576 if (util_format_is_srgb(texture->format)) {

2577 for (int i = 0; i < 3; i++)

2578 border_color[i] =

2579 util_format_linear_to_srgb_float(border_color[i]);

2580 }

2581

2582 /* Turn the border color into the layout of channels that it would

2583 * have when stored as texture contents.

2584 */

2585 float storage_color[4];

2586 util_format_unswizzle_4f(storage_color,

2587 border_color,

2588 tex_format_desc->swizzle);

2589

2590 /* Now, pack so that when the vc4_format-sampled texture contents are

2591 * replaced with our border color, the vc4_get_format_swizzle()

2592 * swizzling will get the right channels.

2593 */

2594 if (util_format_is_depth_or_stencil(texture->format)) {

2595 uc.ui[0] = util_pack_z(PIPE_FORMAT_Z24X8_UNORM,

2596 sampler->border_color.f[0]) << 8;

2597 } else {

2598 switch (rsc->vc4_format) {

2599 default:

2600 case VC4_TEXTURE_TYPE_RGBA8888:

2601 util_pack_color(storage_color,

2602 PIPE_FORMAT_R8G8B8A8_UNORM, &uc);

2603 break;

2604 case VC4_TEXTURE_TYPE_RGBA4444:

2605 util_pack_color(storage_color,

2606 PIPE_FORMAT_A8B8G8R8_UNORM, &uc);

2607 break;

2608 case VC4_TEXTURE_TYPE_RGB565:

2609 util_pack_color(storage_color,

2610 PIPE_FORMAT_B8G8R8A8_UNORM, &uc);

2611 break;

2612 case VC4_TEXTURE_TYPE_ALPHA:

2613 uc.ui[0] = float_to_ubyte(storage_color[0]) << 24;

2614 break;

2615 case VC4_TEXTURE_TYPE_LUMALPHA:

2616 uc.ui[0] = ((float_to_ubyte(storage_color[1]) << 24) |

2617 (float_to_ubyte(storage_color[0]) << 0));

2618 break;

2619 }

2620 }

2621

2622 cl_u32(&vc4->uniforms, uc.ui[0]);

2623 }

2624

2625 static uint32_t

2626 get_texrect_scale(struct vc4_texture_stateobj *texstate,

2627 enum quniform_contents contents,

2628 uint32_t data)

2629 {

2630 struct pipe_sampler_view *texture = texstate->textures[data];

2631 uint32_t dim;

2632

2633 if (contents == QUNIFORM_TEXRECT_SCALE_X)

2634 dim = texture->texture->width0;

2635 else

2636 dim = texture->texture->height0;

2637

2638 return fui(1.0f / dim);

2639 }

2640

2641 static struct vc4_bo *

2642 vc4_upload_ubo(struct vc4_context *vc4, struct vc4_compiled_shader *shader,

2643 const uint32_t *gallium_uniforms)

2644 {

2645 if (!shader->ubo_size)

2646 return NULL;

2647

2648 struct vc4_bo *ubo = vc4_bo_alloc(vc4->screen, shader->ubo_size, "ubo");

2649 uint32_t *data = vc4_bo_map(ubo);

2650 for (uint32_t i = 0; i < shader->num_ubo_ranges; i++) {

2651 memcpy(data + shader->ubo_ranges[i].dst_offset,

2652 gallium_uniforms + shader->ubo_ranges[i].src_offset,

2653 shader->ubo_ranges[i].size);

2654 }

2655

2656 return ubo;

2657 }

2658

2659 void

2660 vc4_write_uniforms(struct vc4_context *vc4, struct vc4_compiled_shader *shader,

2661 struct vc4_constbuf_stateobj *cb,

2662 struct vc4_texture_stateobj *texstate)

2663 {

2664 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;

2665 const uint32_t *gallium_uniforms = cb->cb[0].user_buffer;

2666 struct vc4_bo *ubo = vc4_upload_ubo(vc4, shader, gallium_uniforms);

2667

2668 cl_start_shader_reloc(&vc4->uniforms, uinfo->num_texture_samples);

2669

2670 for (int i = 0; i < uinfo->count; i++) {

2671

2672 switch (uinfo->contents[i]) {

2673 case QUNIFORM_CONSTANT:

2674 cl_u32(&vc4->uniforms, uinfo->data[i]);

2675 break;

2676 case QUNIFORM_UNIFORM:

2677 cl_u32(&vc4->uniforms,

2678 gallium_uniforms[uinfo->data[i]]);

2679 break;

2680 case QUNIFORM_VIEWPORT_X_SCALE:

2681 cl_f(&vc4->uniforms, vc4->viewport.scale[0] * 16.0f);

2682 break;

2683 case QUNIFORM_VIEWPORT_Y_SCALE:

2684 cl_f(&vc4->uniforms, vc4->viewport.scale[1] * 16.0f);

2685 break;

2686

2687 case QUNIFORM_VIEWPORT_Z_OFFSET:

2688 cl_f(&vc4->uniforms, vc4->viewport.translate[2]);

2689 break;

2690 case QUNIFORM_VIEWPORT_Z_SCALE:

2691 cl_f(&vc4->uniforms, vc4->viewport.scale[2]);

2692 break;

2693

2694 case QUNIFORM_USER_CLIP_PLANE:

2695 cl_f(&vc4->uniforms,

2696 vc4->clip.ucp[uinfo->data[i] / 4][uinfo->data[i] % 4]);

2697 break;

2698

2699 case QUNIFORM_TEXTURE_CONFIG_P0:

2700 write_texture_p0(vc4, texstate, uinfo->data[i]);

2701 break;

2702

2703 case QUNIFORM_TEXTURE_CONFIG_P1:

2704 write_texture_p1(vc4, texstate, uinfo->data[i]);

2705 break;

2706

2707 case QUNIFORM_TEXTURE_CONFIG_P2:

2708 write_texture_p2(vc4, texstate, uinfo->data[i]);

2709 break;

2710

2711 case QUNIFORM_UBO_ADDR:

2712 cl_reloc(vc4, &vc4->uniforms, ubo, 0);

2713 break;

2714

2715 case QUNIFORM_TEXTURE_BORDER_COLOR:

2716 write_texture_border_color(vc4, texstate, uinfo->data[i]);

2717 break;

2718

2719 case QUNIFORM_TEXRECT_SCALE_X:

2720 case QUNIFORM_TEXRECT_SCALE_Y:

2721 cl_u32(&vc4->uniforms,

2722 get_texrect_scale(texstate,

2723 uinfo->contents[i],

2724 uinfo->data[i]));

2725 break;

2726

2727 case QUNIFORM_BLEND_CONST_COLOR:

2728 cl_f(&vc4->uniforms,

2729 vc4->blend_color.color[uinfo->data[i]]);

2730 break;

2731

2732 case QUNIFORM_STENCIL:

2733 cl_u32(&vc4->uniforms,

2734 vc4->zsa->stencil_uniforms[uinfo->data[i]] |

2735 (uinfo->data[i] <= 1 ?

2736 (vc4->stencil_ref.ref_value[uinfo->data[i]] << 8) :

2737 0));

2738 break;

2739

2740 case QUNIFORM_ALPHA_REF:

2741 cl_f(&vc4->uniforms, vc4->zsa->base.alpha.ref_value);

2742 break;

2743 }

2744 #if 0

2745 uint32_t written_val = *(uint32_t *)(vc4->uniforms.next - 4);

2746 fprintf(stderr, "%p: %d / 0x%08x (%f)\n",

2747 shader, i, written_val, uif(written_val));

2748 #endif

2749 }

2750 }

2751

2752 static void

2753 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)

2754 {

2755 struct vc4_context *vc4 = vc4_context(pctx);

2756 vc4->prog.bind_fs = hwcso;

2757 vc4->prog.dirty |= VC4_SHADER_DIRTY_FP;

2758 vc4->dirty |= VC4_DIRTY_PROG;

2759 }

2760

2761 static void

2762 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)

2763 {

2764 struct vc4_context *vc4 = vc4_context(pctx);

2765 vc4->prog.bind_vs = hwcso;

2766 vc4->prog.dirty |= VC4_SHADER_DIRTY_VP;

2767 vc4->dirty |= VC4_DIRTY_PROG;

2768 }

2769

2770 void

2771 vc4_program_init(struct pipe_context *pctx)

2772 {

2773 struct vc4_context *vc4 = vc4_context(pctx);

2774

2775 pctx->create_vs_state = vc4_shader_state_create;

2776 pctx->delete_vs_state = vc4_shader_state_delete;

2777

2778 pctx->create_fs_state = vc4_shader_state_create;

2779 pctx->delete_fs_state = vc4_shader_state_delete;

2780

2781 pctx->bind_fs_state = vc4_fp_state_bind;

2782 pctx->bind_vs_state = vc4_vp_state_bind;

2783

2784 vc4->fs_cache = _mesa_hash_table_create(pctx, fs_cache_hash,

2785 fs_cache_compare);

2786 vc4->vs_cache = _mesa_hash_table_create(pctx, vs_cache_hash,

2787 vs_cache_compare);

2788 }

2789

2790 void

2791 vc4_program_fini(struct pipe_context *pctx)

2792 {

2793 struct vc4_context *vc4 = vc4_context(pctx);

2794

2795 struct hash_entry *entry;

2796 hash_table_foreach(vc4->fs_cache, entry) {

2797 struct vc4_compiled_shader *shader = entry->data;

2798 vc4_bo_unreference(&shader->bo);

2799 ralloc_free(shader);

2800 _mesa_hash_table_remove(vc4->fs_cache, entry);

2801 }

2802

2803 hash_table_foreach(vc4->vs_cache, entry) {

2804 struct vc4_compiled_shader *shader = entry->data;

2805 vc4_bo_unreference(&shader->bo);

2806 ralloc_free(shader);

2807 _mesa_hash_table_remove(vc4->vs_cache, entry);

2808 }

2809 }