i965/gen6-7: Implement stall and flushes required prior to switching pipelines.
authorFrancisco Jerez <currojerez@riseup.net>
Sun, 3 Jan 2016 03:02:09 +0000 (19:02 -0800)
committerFrancisco Jerez <currojerez@riseup.net>
Fri, 15 Jan 2016 03:26:23 +0000 (19:26 -0800)
commit18c76551ee425b981efefc61f663a7781df17882
tree18a152e0659c7245aa13d2922e271cd148198b79
parent044acb9256046bebec890cac7e42043754459fc2
i965/gen6-7: Implement stall and flushes required prior to switching pipelines.

Switching the current pipeline while it's not completely idle or the
read and write caches aren't flushed can lead to corruption.  Fixes
misrendering of at least the following Khronos CTS test:

 ES31-CTS.shader_image_load_store.basic-allTargets-store-fs

The stall and flushes are no longer required on Gen8+.

v2: Emit PIPE_CONTROL with non-zero post-sync op before the write
    cache flush on SNB due to hardware bug. (Ken)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93323
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
src/mesa/drivers/dri/i965/brw_misc_state.c