git.libre-soc.org Git - openpower-isa.git/blob

1 # SPDX-License-Identifier: LGPLv3+

4 # Funded by NLnet http://nlnet.nl

5 """core of the python-based POWER9 simulator

7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is

8 not speed, it is for both learning and educational purposes, as well as

9 a method of verifying the HDL.

11 related bugs:

13 * https://bugs.libre-soc.org/show_bug.cgi?id=424

14 """

16 from nmigen.back.pysim import Settle

17 from functools import wraps

18 from copy import copy

19 from openpower.decoder.orderedset import OrderedSet

20 from openpower.decoder.selectable_int import (FieldSelectableInt, SelectableInt,

21 selectconcat)

22 from openpower.decoder.power_enums import (spr_dict, spr_byname, XER_bits,

23 insns, MicrOp, In1Sel, In2Sel, In3Sel,

24 OutSel, CROutSel,

25 SVP64RMMode, SVP64PredMode,

26 SVP64PredInt, SVP64PredCR)

28 from openpower.decoder.power_enums import SVPtype

30 from openpower.decoder.helpers import exts, gtu, ltu, undefined

31 from openpower.consts import PIb, MSRb # big-endian (PowerISA versions)

32 from openpower.consts import SVP64CROffs

33 from openpower.decoder.power_svp64 import SVP64RM, decode_extra

35 from openpower.decoder.isa.radixmmu import RADIX

36 from openpower.decoder.isa.mem import Mem, swap_order

38 from collections import namedtuple

39 import math

40 import sys

42 instruction_info = namedtuple('instruction_info',

43 'func read_regs uninit_regs write_regs ' +

44 'special_regs op_fields form asmregs')

46 special_sprs = {

47 'LR': 8,

48 'CTR': 9,

49 'TAR': 815,

50 'XER': 1,

51 'VRSAVE': 256}

54 REG_SORT_ORDER = {

55 # TODO (lkcl): adjust other registers that should be in a particular order

56 # probably CA, CA32, and CR

57 "RT": 0,

58 "RA": 0,

59 "RB": 0,

60 "RS": 0,

61 "CR": 0,

62 "LR": 0,

63 "CTR": 0,

64 "TAR": 0,

65 "CA": 0,

66 "CA32": 0,

67 "MSR": 0,

68 "SVSTATE": 0,

70 "overflow": 1,

71 }

74 def create_args(reglist, extra=None):

75 retval = list(OrderedSet(reglist))

76 retval.sort(key=lambda reg: REG_SORT_ORDER[reg])

77 if extra is not None:

78 return [extra] + retval

79 return retval

83 class GPR(dict):

84 def __init__(self, decoder, isacaller, svstate, regfile):

85 dict.__init__(self)

86 self.sd = decoder

87 self.isacaller = isacaller

88 self.svstate = svstate

89 for i in range(32):

90 self[i] = SelectableInt(regfile[i], 64)

92 def __call__(self, ridx):

93 return self[ridx]

95 def set_form(self, form):

96 self.form = form

98 def getz(self, rnum):

99 # rnum = rnum.value # only SelectableInt allowed

100 print("GPR getzero?", rnum)

101 if rnum == 0:

102 return SelectableInt(0, 64)

103 return self[rnum]

104

105 def _get_regnum(self, attr):

106 getform = self.sd.sigforms[self.form]

107 rnum = getattr(getform, attr)

108 return rnum

109

110 def ___getitem__(self, attr):

111 """ XXX currently not used

112 """

113 rnum = self._get_regnum(attr)

114 offs = self.svstate.srcstep

115 print("GPR getitem", attr, rnum, "srcoffs", offs)

116 return self.regfile[rnum]

117

118 def dump(self):

119 for i in range(0, len(self), 8):

120 s = []

121 for j in range(8):

122 s.append("%08x" % self[i+j].value)

123 s = ' '.join(s)

124 print("reg", "%2d" % i, s)

125

126

127 class SPR(dict):

128 def __init__(self, dec2, initial_sprs={}):

129 self.sd = dec2

130 dict.__init__(self)

131 for key, v in initial_sprs.items():

132 if isinstance(key, SelectableInt):

133 key = key.value

134 key = special_sprs.get(key, key)

135 if isinstance(key, int):

136 info = spr_dict[key]

137 else:

138 info = spr_byname[key]

139 if not isinstance(v, SelectableInt):

140 v = SelectableInt(v, info.length)

141 self[key] = v

142

143 def __getitem__(self, key):

144 print("get spr", key)

145 print("dict", self.items())

146 # if key in special_sprs get the special spr, otherwise return key

147 if isinstance(key, SelectableInt):

148 key = key.value

149 if isinstance(key, int):

150 key = spr_dict[key].SPR

151 key = special_sprs.get(key, key)

152 if key == 'HSRR0': # HACK!

153 key = 'SRR0'

154 if key == 'HSRR1': # HACK!

155 key = 'SRR1'

156 if key in self:

157 res = dict.__getitem__(self, key)

158 else:

159 if isinstance(key, int):

160 info = spr_dict[key]

161 else:

162 info = spr_byname[key]

163 dict.__setitem__(self, key, SelectableInt(0, info.length))

164 res = dict.__getitem__(self, key)

165 print("spr returning", key, res)

166 return res

167

168 def __setitem__(self, key, value):

169 if isinstance(key, SelectableInt):

170 key = key.value

171 if isinstance(key, int):

172 key = spr_dict[key].SPR

173 print("spr key", key)

174 key = special_sprs.get(key, key)

175 if key == 'HSRR0': # HACK!

176 self.__setitem__('SRR0', value)

177 if key == 'HSRR1': # HACK!

178 self.__setitem__('SRR1', value)

179 print("setting spr", key, value)

180 dict.__setitem__(self, key, value)

181

182 def __call__(self, ridx):

183 return self[ridx]

184

185

186 class PC:

187 def __init__(self, pc_init=0):

188 self.CIA = SelectableInt(pc_init, 64)

189 self.NIA = self.CIA + SelectableInt(4, 64) # only true for v3.0B!

190

191 def update_nia(self, is_svp64):

192 increment = 8 if is_svp64 else 4

193 self.NIA = self.CIA + SelectableInt(increment, 64)

194

195 def update(self, namespace, is_svp64):

196 """updates the program counter (PC) by 4 if v3.0B mode or 8 if SVP64

197 """

198 self.CIA = namespace['NIA'].narrow(64)

199 self.update_nia(is_svp64)

200 namespace['CIA'] = self.CIA

201 namespace['NIA'] = self.NIA

202

203

204 # Simple-V: see https://libre-soc.org/openpower/sv

205 class SVP64State:

206 def __init__(self, init=0):

207 self.spr = SelectableInt(init, 32)

208 # fields of SVSTATE, see https://libre-soc.org/openpower/sv/sprs/

209 self.maxvl = FieldSelectableInt(self.spr, tuple(range(0,7)))

210 self.vl = FieldSelectableInt(self.spr, tuple(range(7,14)))

211 self.srcstep = FieldSelectableInt(self.spr, tuple(range(14,21)))

212 self.dststep = FieldSelectableInt(self.spr, tuple(range(21,28)))

213 self.subvl = FieldSelectableInt(self.spr, tuple(range(28,30)))

214 self.svstep = FieldSelectableInt(self.spr, tuple(range(30,32)))

215

216

217 # SVP64 ReMap field

218 class SVP64RMFields:

219 def __init__(self, init=0):

220 self.spr = SelectableInt(init, 24)

221 # SVP64 RM fields: see https://libre-soc.org/openpower/sv/svp64/

222 self.mmode = FieldSelectableInt(self.spr, [0])

223 self.mask = FieldSelectableInt(self.spr, tuple(range(1,4)))

224 self.elwidth = FieldSelectableInt(self.spr, tuple(range(4,6)))

225 self.ewsrc = FieldSelectableInt(self.spr, tuple(range(6,8)))

226 self.subvl = FieldSelectableInt(self.spr, tuple(range(8,10)))

227 self.extra = FieldSelectableInt(self.spr, tuple(range(10,19)))

228 self.mode = FieldSelectableInt(self.spr, tuple(range(19,24)))

229 # these cover the same extra field, split into parts as EXTRA2

230 self.extra2 = list(range(4))

231 self.extra2[0] = FieldSelectableInt(self.spr, tuple(range(10,12)))

232 self.extra2[1] = FieldSelectableInt(self.spr, tuple(range(12,14)))

233 self.extra2[2] = FieldSelectableInt(self.spr, tuple(range(14,16)))

234 self.extra2[3] = FieldSelectableInt(self.spr, tuple(range(16,18)))

235 self.smask = FieldSelectableInt(self.spr, tuple(range(16,19)))

236 # and here as well, but EXTRA3

237 self.extra3 = list(range(3))

238 self.extra3[0] = FieldSelectableInt(self.spr, tuple(range(10,13)))

239 self.extra3[1] = FieldSelectableInt(self.spr, tuple(range(13,16)))

240 self.extra3[2] = FieldSelectableInt(self.spr, tuple(range(16,19)))

241

242

243 SVP64RM_MMODE_SIZE = len(SVP64RMFields().mmode.br)

244 SVP64RM_MASK_SIZE = len(SVP64RMFields().mask.br)

245 SVP64RM_ELWIDTH_SIZE = len(SVP64RMFields().elwidth.br)

246 SVP64RM_EWSRC_SIZE = len(SVP64RMFields().ewsrc.br)

247 SVP64RM_SUBVL_SIZE = len(SVP64RMFields().subvl.br)

248 SVP64RM_EXTRA2_SPEC_SIZE = len(SVP64RMFields().extra2[0].br)

249 SVP64RM_EXTRA3_SPEC_SIZE = len(SVP64RMFields().extra3[0].br)

250 SVP64RM_SMASK_SIZE = len(SVP64RMFields().smask.br)

251 SVP64RM_MODE_SIZE = len(SVP64RMFields().mode.br)

252

253

254 # SVP64 Prefix fields: see https://libre-soc.org/openpower/sv/svp64/

255 class SVP64PrefixFields:

256 def __init__(self):

257 self.insn = SelectableInt(0, 32)

258 # 6 bit major opcode EXT001, 2 bits "identifying" (7, 9), 24 SV ReMap

259 self.major = FieldSelectableInt(self.insn, tuple(range(0,6)))

260 self.pid = FieldSelectableInt(self.insn, (7, 9)) # must be 0b11

261 rmfields = [6, 8] + list(range(10,32)) # SVP64 24-bit RM (ReMap)

262 self.rm = FieldSelectableInt(self.insn, rmfields)

263

264

265 SV64P_MAJOR_SIZE = len(SVP64PrefixFields().major.br)

266 SV64P_PID_SIZE = len(SVP64PrefixFields().pid.br)

267 SV64P_RM_SIZE = len(SVP64PrefixFields().rm.br)

268

269 # decode SVP64 predicate integer to reg number and invert

270 def get_predint(gpr, mask):

271 r10 = gpr(10)

272 r30 = gpr(30)

273 print ("get_predint", mask, SVP64PredInt.ALWAYS.value)

274 if mask == SVP64PredInt.ALWAYS.value:

275 return 0xffff_ffff_ffff_ffff

276 if mask == SVP64PredInt.R3_UNARY.value:

277 return 1 << (gpr(3).value & 0b111111)

278 if mask == SVP64PredInt.R3.value:

279 return gpr(3).value

280 if mask == SVP64PredInt.R3_N.value:

281 return ~gpr(3).value

282 if mask == SVP64PredInt.R10.value:

283 return gpr(10).value

284 if mask == SVP64PredInt.R10_N.value:

285 return ~gpr(10).value

286 if mask == SVP64PredInt.R30.value:

287 return gpr(30).value

288 if mask == SVP64PredInt.R30_N.value:

289 return ~gpr(30).value

290

291 # decode SVP64 predicate CR to reg number and invert status

292 def _get_predcr(mask):

293 if mask == SVP64PredCR.LT.value:

294 return 0, 1

295 if mask == SVP64PredCR.GE.value:

296 return 0, 0

297 if mask == SVP64PredCR.GT.value:

298 return 1, 1

299 if mask == SVP64PredCR.LE.value:

300 return 1, 0

301 if mask == SVP64PredCR.EQ.value:

302 return 2, 1

303 if mask == SVP64PredCR.NE.value:

304 return 2, 0

305 if mask == SVP64PredCR.SO.value:

306 return 3, 1

307 if mask == SVP64PredCR.NS.value:

308 return 3, 0

309

310 # read individual CR fields (0..VL-1), extract the required bit

311 # and construct the mask

312 def get_predcr(crl, mask, vl):

313 idx, noninv = _get_predcr(mask)

314 mask = 0

315 for i in range(vl):

316 cr = crl[i+SVP64CROffs.CRPred]

317 if cr[idx].value == noninv:

318 mask |= (1<<i)

319 return mask

320

321

322 def get_pdecode_idx_in(dec2, name):

323 op = dec2.dec.op

324 in1_sel = yield op.in1_sel

325 in2_sel = yield op.in2_sel

326 in3_sel = yield op.in3_sel

327 # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)

328 in1 = yield dec2.e.read_reg1.data

329 in2 = yield dec2.e.read_reg2.data

330 in3 = yield dec2.e.read_reg3.data

331 in1_isvec = yield dec2.in1_isvec

332 in2_isvec = yield dec2.in2_isvec

333 in3_isvec = yield dec2.in3_isvec

334 print ("get_pdecode_idx_in in1", name, in1_sel, In1Sel.RA.value,

335 in1, in1_isvec)

336 print ("get_pdecode_idx_in in2", name, in2_sel, In2Sel.RB.value,

337 in2, in2_isvec)

338 print ("get_pdecode_idx_in in3", name, in3_sel, In3Sel.RS.value,

339 in3, in3_isvec)

340 # identify which regnames map to in1/2/3

341 if name == 'RA':

342 if (in1_sel == In1Sel.RA.value or

343 (in1_sel == In1Sel.RA_OR_ZERO.value and in1 != 0)):

344 return in1, in1_isvec

345 if in1_sel == In1Sel.RA_OR_ZERO.value:

346 return in1, in1_isvec

347 elif name == 'RB':

348 if in2_sel == In2Sel.RB.value:

349 return in2, in2_isvec

350 if in3_sel == In3Sel.RB.value:

351 return in3, in3_isvec

352 # XXX TODO, RC doesn't exist yet!

353 elif name == 'RC':

354 assert False, "RC does not exist yet"

355 elif name == 'RS':

356 if in1_sel == In1Sel.RS.value:

357 return in1, in1_isvec

358 if in2_sel == In2Sel.RS.value:

359 return in2, in2_isvec

360 if in3_sel == In3Sel.RS.value:

361 return in3, in3_isvec

362 return None, False

363

364

365 def get_pdecode_cr_out(dec2, name):

366 op = dec2.dec.op

367 out_sel = yield op.cr_out

368 out_bitfield = yield dec2.dec_cr_out.cr_bitfield.data

369 sv_cr_out = yield op.sv_cr_out

370 spec = yield dec2.crout_svdec.spec

371 sv_override = yield dec2.dec_cr_out.sv_override

372 # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)

373 out = yield dec2.e.write_cr.data

374 o_isvec = yield dec2.o_isvec

375 print ("get_pdecode_cr_out", out_sel, CROutSel.CR0.value, out, o_isvec)

376 print (" sv_cr_out", sv_cr_out)

377 print (" cr_bf", out_bitfield)

378 print (" spec", spec)

379 print (" override", sv_override)

380 # identify which regnames map to out / o2

381 if name == 'CR0':

382 if out_sel == CROutSel.CR0.value:

383 return out, o_isvec

384 print ("get_pdecode_idx_out not found", name)

385 return None, False

386

387

388 def get_pdecode_idx_out(dec2, name):

389 op = dec2.dec.op

390 out_sel = yield op.out_sel

391 # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)

392 out = yield dec2.e.write_reg.data

393 o_isvec = yield dec2.o_isvec

394 # identify which regnames map to out / o2

395 if name == 'RA':

396 print ("get_pdecode_idx_out", out_sel, OutSel.RA.value, out, o_isvec)

397 if out_sel == OutSel.RA.value:

398 return out, o_isvec

399 elif name == 'RT':

400 print ("get_pdecode_idx_out", out_sel, OutSel.RT.value,

401 OutSel.RT_OR_ZERO.value, out, o_isvec)

402 if out_sel == OutSel.RT.value:

403 return out, o_isvec

404 print ("get_pdecode_idx_out not found", name)

405 return None, False

406

407

408 # XXX TODO

409 def get_pdecode_idx_out2(dec2, name):

410 op = dec2.dec.op

411 print ("TODO: get_pdecode_idx_out2", name)

412 return None, False

413

414

415 class ISACaller:

416 # decoder2 - an instance of power_decoder2

417 # regfile - a list of initial values for the registers

418 # initial_{etc} - initial values for SPRs, Condition Register, Mem, MSR

419 # respect_pc - tracks the program counter. requires initial_insns

420 def __init__(self, decoder2, regfile, initial_sprs=None, initial_cr=0,

421 initial_mem=None, initial_msr=0,

422 initial_svstate=0,

423 initial_insns=None, respect_pc=False,

424 disassembly=None,

425 initial_pc=0,

426 bigendian=False,

427 mmu=False,

428 icachemmu=False):

429

430 self.bigendian = bigendian

431 self.halted = False

432 self.is_svp64_mode = False

433 self.respect_pc = respect_pc

434 if initial_sprs is None:

435 initial_sprs = {}

436 if initial_mem is None:

437 initial_mem = {}

438 if initial_insns is None:

439 initial_insns = {}

440 assert self.respect_pc == False, "instructions required to honor pc"

441

442 print("ISACaller insns", respect_pc, initial_insns, disassembly)

443 print("ISACaller initial_msr", initial_msr)

444

445 # "fake program counter" mode (for unit testing)

446 self.fake_pc = 0

447 disasm_start = 0

448 if not respect_pc:

449 if isinstance(initial_mem, tuple):

450 self.fake_pc = initial_mem[0]

451 disasm_start = self.fake_pc

452 else:

453 disasm_start = initial_pc

454

455 # disassembly: we need this for now (not given from the decoder)

456 self.disassembly = {}

457 if disassembly:

458 for i, code in enumerate(disassembly):

459 self.disassembly[i*4 + disasm_start] = code

460

461 # set up registers, instruction memory, data memory, PC, SPRs, MSR

462 self.svp64rm = SVP64RM()

463 if initial_svstate is None:

464 initial_svstate = 0

465 if isinstance(initial_svstate, int):

466 initial_svstate = SVP64State(initial_svstate)

467 self.svstate = initial_svstate

468 self.gpr = GPR(decoder2, self, self.svstate, regfile)

469 self.spr = SPR(decoder2, initial_sprs) # initialise SPRs before MMU

470 self.mem = Mem(row_bytes=8, initial_mem=initial_mem)

471 self.imem = Mem(row_bytes=4, initial_mem=initial_insns)

472 # MMU mode, redirect underlying Mem through RADIX

473 self.msr = SelectableInt(initial_msr, 64) # underlying reg

474 if mmu:

475 self.mem = RADIX(self.mem, self)

476 if icachemmu:

477 self.imem = RADIX(self.imem, self)

478 self.pc = PC()

479

480 # TODO, needed here:

481 # FPR (same as GPR except for FP nums)

482 # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)

483 # note that mffs, mcrfs, mtfsf "manage" this FPSCR

484 # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)

485 # note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs

486 # -- Done

487 # 2.3.2 LR (actually SPR #8) -- Done

488 # 2.3.3 CTR (actually SPR #9) -- Done

489 # 2.3.4 TAR (actually SPR #815)

490 # 3.2.2 p45 XER (actually SPR #1) -- Done

491 # 3.2.3 p46 p232 VRSAVE (actually SPR #256)

492

493 # create CR then allow portions of it to be "selectable" (below)

494 #rev_cr = int('{:016b}'.format(initial_cr)[::-1], 2)

495 self.cr = SelectableInt(initial_cr, 64) # underlying reg

496 #self.cr = FieldSelectableInt(self._cr, list(range(32, 64)))

497

498 # "undefined", just set to variable-bit-width int (use exts "max")

499 #self.undefined = SelectableInt(0, 256) # TODO, not hard-code 256!

500

501 self.namespace = {}

502 self.namespace.update(self.spr)

503 self.namespace.update({'GPR': self.gpr,

504 'MEM': self.mem,

505 'SPR': self.spr,

506 'memassign': self.memassign,

507 'NIA': self.pc.NIA,

508 'CIA': self.pc.CIA,

509 'SVSTATE': self.svstate.spr,

510 'CR': self.cr,

511 'MSR': self.msr,

512 'undefined': undefined,

513 'mode_is_64bit': True,

514 'SO': XER_bits['SO']

515 })

516

517 # update pc to requested start point

518 self.set_pc(initial_pc)

519

520 # field-selectable versions of Condition Register TODO check bitranges?

521 self.crl = []

522 for i in range(8):

523 bits = tuple(range(i*4+32, (i+1)*4+32)) # errr... maybe?

524 _cr = FieldSelectableInt(self.cr, bits)

525 self.crl.append(_cr)

526 self.namespace["CR%d" % i] = _cr

527

528 self.decoder = decoder2.dec

529 self.dec2 = decoder2

530

531 def TRAP(self, trap_addr=0x700, trap_bit=PIb.TRAP):

532 print("TRAP:", hex(trap_addr), hex(self.namespace['MSR'].value))

533 # store CIA(+4?) in SRR0, set NIA to 0x700

534 # store MSR in SRR1, set MSR to um errr something, have to check spec

535 self.spr['SRR0'].value = self.pc.CIA.value

536 self.spr['SRR1'].value = self.namespace['MSR'].value

537 self.trap_nia = SelectableInt(trap_addr, 64)

538 self.spr['SRR1'][trap_bit] = 1 # change *copy* of MSR in SRR1

539

540 # set exception bits. TODO: this should, based on the address

541 # in figure 66 p1065 V3.0B and the table figure 65 p1063 set these

542 # bits appropriately. however it turns out that *for now* in all

543 # cases (all trap_addrs) the exact same thing is needed.

544 self.msr[MSRb.IR] = 0

545 self.msr[MSRb.DR] = 0

546 self.msr[MSRb.FE0] = 0

547 self.msr[MSRb.FE1] = 0

548 self.msr[MSRb.EE] = 0

549 self.msr[MSRb.RI] = 0

550 self.msr[MSRb.SF] = 1

551 self.msr[MSRb.TM] = 0

552 self.msr[MSRb.VEC] = 0

553 self.msr[MSRb.VSX] = 0

554 self.msr[MSRb.PR] = 0

555 self.msr[MSRb.FP] = 0

556 self.msr[MSRb.PMM] = 0

557 self.msr[MSRb.TEs] = 0

558 self.msr[MSRb.TEe] = 0

559 self.msr[MSRb.UND] = 0

560 self.msr[MSRb.LE] = 1

561

562 def memassign(self, ea, sz, val):

563 self.mem.memassign(ea, sz, val)

564

565 def prep_namespace(self, formname, op_fields):

566 # TODO: get field names from form in decoder*1* (not decoder2)

567 # decoder2 is hand-created, and decoder1.sigform is auto-generated

568 # from spec

569 # then "yield" fields only from op_fields rather than hard-coded

570 # list, here.

571 fields = self.decoder.sigforms[formname]

572 for name in op_fields:

573 if name == 'spr':

574 sig = getattr(fields, name.upper())

575 else:

576 sig = getattr(fields, name)

577 val = yield sig

578 # these are all opcode fields involved in index-selection of CR,

579 # and need to do "standard" arithmetic. CR[BA+32] for example

580 # would, if using SelectableInt, only be 5-bit.

581 if name in ['BF', 'BFA', 'BC', 'BA', 'BB', 'BT', 'BI']:

582 self.namespace[name] = val

583 else:

584 self.namespace[name] = SelectableInt(val, sig.width)

585

586 self.namespace['XER'] = self.spr['XER']

587 self.namespace['CA'] = self.spr['XER'][XER_bits['CA']].value

588 self.namespace['CA32'] = self.spr['XER'][XER_bits['CA32']].value

589

590 def handle_carry_(self, inputs, outputs, already_done):

591 inv_a = yield self.dec2.e.do.invert_in

592 if inv_a:

593 inputs[0] = ~inputs[0]

594

595 imm_ok = yield self.dec2.e.do.imm_data.ok

596 if imm_ok:

597 imm = yield self.dec2.e.do.imm_data.data

598 inputs.append(SelectableInt(imm, 64))

599 assert len(outputs) >= 1

600 print("outputs", repr(outputs))

601 if isinstance(outputs, list) or isinstance(outputs, tuple):

602 output = outputs[0]

603 else:

604 output = outputs

605 gts = []

606 for x in inputs:

607 print("gt input", x, output)

608 gt = (gtu(x, output))

609 gts.append(gt)

610 print(gts)

611 cy = 1 if any(gts) else 0

612 print("CA", cy, gts)

613 if not (1 & already_done):

614 self.spr['XER'][XER_bits['CA']] = cy

615

616 print("inputs", already_done, inputs)

617 # 32 bit carry

618 # ARGH... different for OP_ADD... *sigh*...

619 op = yield self.dec2.e.do.insn_type

620 if op == MicrOp.OP_ADD.value:

621 res32 = (output.value & (1 << 32)) != 0

622 a32 = (inputs[0].value & (1 << 32)) != 0

623 if len(inputs) >= 2:

624 b32 = (inputs[1].value & (1 << 32)) != 0

625 else:

626 b32 = False

627 cy32 = res32 ^ a32 ^ b32

628 print("CA32 ADD", cy32)

629 else:

630 gts = []

631 for x in inputs:

632 print("input", x, output)

633 print(" x[32:64]", x, x[32:64])

634 print(" o[32:64]", output, output[32:64])

635 gt = (gtu(x[32:64], output[32:64])) == SelectableInt(1, 1)

636 gts.append(gt)

637 cy32 = 1 if any(gts) else 0

638 print("CA32", cy32, gts)

639 if not (2 & already_done):

640 self.spr['XER'][XER_bits['CA32']] = cy32

641

642 def handle_overflow(self, inputs, outputs, div_overflow):

643 if hasattr(self.dec2.e.do, "invert_in"):

644 inv_a = yield self.dec2.e.do.invert_in

645 if inv_a:

646 inputs[0] = ~inputs[0]

647

648 imm_ok = yield self.dec2.e.do.imm_data.ok

649 if imm_ok:

650 imm = yield self.dec2.e.do.imm_data.data

651 inputs.append(SelectableInt(imm, 64))

652 assert len(outputs) >= 1

653 print("handle_overflow", inputs, outputs, div_overflow)

654 if len(inputs) < 2 and div_overflow is None:

655 return

656

657 # div overflow is different: it's returned by the pseudo-code

658 # because it's more complex than can be done by analysing the output

659 if div_overflow is not None:

660 ov, ov32 = div_overflow, div_overflow

661 # arithmetic overflow can be done by analysing the input and output

662 elif len(inputs) >= 2:

663 output = outputs[0]

664

665 # OV (64-bit)

666 input_sgn = [exts(x.value, x.bits) < 0 for x in inputs]

667 output_sgn = exts(output.value, output.bits) < 0

668 ov = 1 if input_sgn[0] == input_sgn[1] and \

669 output_sgn != input_sgn[0] else 0

670

671 # OV (32-bit)

672 input32_sgn = [exts(x.value, 32) < 0 for x in inputs]

673 output32_sgn = exts(output.value, 32) < 0

674 ov32 = 1 if input32_sgn[0] == input32_sgn[1] and \

675 output32_sgn != input32_sgn[0] else 0

676

677 self.spr['XER'][XER_bits['OV']] = ov

678 self.spr['XER'][XER_bits['OV32']] = ov32

679 so = self.spr['XER'][XER_bits['SO']]

680 so = so | ov

681 self.spr['XER'][XER_bits['SO']] = so

682

683 def handle_comparison(self, outputs, cr_idx=0):

684 out = outputs[0]

685 assert isinstance(out, SelectableInt), \

686 "out zero not a SelectableInt %s" % repr(outputs)

687 print("handle_comparison", out.bits, hex(out.value))

688 # TODO - XXX *processor* in 32-bit mode

689 # https://bugs.libre-soc.org/show_bug.cgi?id=424

690 # if is_32bit:

691 # o32 = exts(out.value, 32)

692 # print ("handle_comparison exts 32 bit", hex(o32))

693 out = exts(out.value, out.bits)

694 print("handle_comparison exts", hex(out))

695 zero = SelectableInt(out == 0, 1)

696 positive = SelectableInt(out > 0, 1)

697 negative = SelectableInt(out < 0, 1)

698 SO = self.spr['XER'][XER_bits['SO']]

699 print("handle_comparison SO", SO)

700 cr_field = selectconcat(negative, positive, zero, SO)

701 self.crl[cr_idx].eq(cr_field)

702

703 def set_pc(self, pc_val):

704 self.namespace['NIA'] = SelectableInt(pc_val, 64)

705 self.pc.update(self.namespace, self.is_svp64_mode)

706

707 def setup_one(self):

708 """set up one instruction

709 """

710 if self.respect_pc:

711 pc = self.pc.CIA.value

712 else:

713 pc = self.fake_pc

714 self._pc = pc

715 ins = self.imem.ld(pc, 4, False, True, instr_fetch=True)

716 if ins is None:

717 raise KeyError("no instruction at 0x%x" % pc)

718 print("setup: 0x%x 0x%x %s" % (pc, ins & 0xffffffff, bin(ins)))

719 print("CIA NIA", self.respect_pc, self.pc.CIA.value, self.pc.NIA.value)

720

721 yield self.dec2.sv_rm.eq(0)

722 yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff)

723 yield self.dec2.dec.bigendian.eq(self.bigendian)

724 yield self.dec2.state.msr.eq(self.msr.value)

725 yield self.dec2.state.pc.eq(pc)

726 if self.svstate is not None:

727 yield self.dec2.state.svstate.eq(self.svstate.spr.value)

728

729 # SVP64. first, check if the opcode is EXT001, and SVP64 id bits set

730 yield Settle()

731 opcode = yield self.dec2.dec.opcode_in

732 pfx = SVP64PrefixFields() # TODO should probably use SVP64PrefixDecoder

733 pfx.insn.value = opcode

734 major = pfx.major.asint(msb0=True) # MSB0 inversion

735 print ("prefix test: opcode:", major, bin(major),

736 pfx.insn[7] == 0b1, pfx.insn[9] == 0b1)

737 self.is_svp64_mode = ((major == 0b000001) and

738 pfx.insn[7].value == 0b1 and

739 pfx.insn[9].value == 0b1)

740 self.pc.update_nia(self.is_svp64_mode)

741 self.namespace['NIA'] = self.pc.NIA

742 self.namespace['SVSTATE'] = self.svstate.spr

743 if not self.is_svp64_mode:

744 return

745

746 # in SVP64 mode. decode/print out svp64 prefix, get v3.0B instruction

747 print ("svp64.rm", bin(pfx.rm.asint(msb0=True)))

748 print (" svstate.vl", self.svstate.vl.asint(msb0=True))

749 print (" svstate.mvl", self.svstate.maxvl.asint(msb0=True))

750 sv_rm = pfx.rm.asint(msb0=True)

751 ins = self.imem.ld(pc+4, 4, False, True, instr_fetch=True)

752 print(" svsetup: 0x%x 0x%x %s" % (pc+4, ins & 0xffffffff, bin(ins)))

753 yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff) # v3.0B suffix

754 yield self.dec2.sv_rm.eq(sv_rm) # svp64 prefix

755 yield Settle()

756

757 def execute_one(self):

758 """execute one instruction

759 """

760 # get the disassembly code for this instruction

761 if self.is_svp64_mode:

762 code = self.disassembly[self._pc+4]

763 print(" svp64 sim-execute", hex(self._pc), code)

764 else:

765 code = self.disassembly[self._pc]

766 print("sim-execute", hex(self._pc), code)

767 opname = code.split(' ')[0]

768 yield from self.call(opname)

769

770 # don't use this except in special circumstances

771 if not self.respect_pc:

772 self.fake_pc += 4

773

774 print("execute one, CIA NIA", self.pc.CIA.value, self.pc.NIA.value)

775

776 def get_assembly_name(self):

777 # TODO, asmregs is from the spec, e.g. add RT,RA,RB

778 # see http://bugs.libre-riscv.org/show_bug.cgi?id=282

779 dec_insn = yield self.dec2.e.do.insn

780 asmcode = yield self.dec2.dec.op.asmcode

781 print("get assembly name asmcode", asmcode, hex(dec_insn))

782 asmop = insns.get(asmcode, None)

783 int_op = yield self.dec2.dec.op.internal_op

784

785 # sigh reconstruct the assembly instruction name

786 if hasattr(self.dec2.e.do, "oe"):

787 ov_en = yield self.dec2.e.do.oe.oe

788 ov_ok = yield self.dec2.e.do.oe.ok

789 else:

790 ov_en = False

791 ov_ok = False

792 if hasattr(self.dec2.e.do, "rc"):

793 rc_en = yield self.dec2.e.do.rc.rc

794 rc_ok = yield self.dec2.e.do.rc.ok

795 else:

796 rc_en = False

797 rc_ok = False

798 # grrrr have to special-case MUL op (see DecodeOE)

799 print("ov %d en %d rc %d en %d op %d" %

800 (ov_ok, ov_en, rc_ok, rc_en, int_op))

801 if int_op in [MicrOp.OP_MUL_H64.value, MicrOp.OP_MUL_H32.value]:

802 print("mul op")

803 if rc_en & rc_ok:

804 asmop += "."

805 else:

806 if not asmop.endswith("."): # don't add "." to "andis."

807 if rc_en & rc_ok:

808 asmop += "."

809 if hasattr(self.dec2.e.do, "lk"):

810 lk = yield self.dec2.e.do.lk

811 if lk:

812 asmop += "l"

813 print("int_op", int_op)

814 if int_op in [MicrOp.OP_B.value, MicrOp.OP_BC.value]:

815 AA = yield self.dec2.dec.fields.FormI.AA[0:-1]

816 print("AA", AA)

817 if AA:

818 asmop += "a"

819 spr_msb = yield from self.get_spr_msb()

820 if int_op == MicrOp.OP_MFCR.value:

821 if spr_msb:

822 asmop = 'mfocrf'

823 else:

824 asmop = 'mfcr'

825 # XXX TODO: for whatever weird reason this doesn't work

826 # https://bugs.libre-soc.org/show_bug.cgi?id=390

827 if int_op == MicrOp.OP_MTCRF.value:

828 if spr_msb:

829 asmop = 'mtocrf'

830 else:

831 asmop = 'mtcrf'

832 return asmop

833

834 def get_spr_msb(self):

835 dec_insn = yield self.dec2.e.do.insn

836 return dec_insn & (1 << 20) != 0 # sigh - XFF.spr[-1]?

837

838 def call(self, name):

839 """call(opcode) - the primary execution point for instructions

840 """

841 name = name.strip() # remove spaces if not already done so

842 if self.halted:

843 print("halted - not executing", name)

844 return

845

846 # TODO, asmregs is from the spec, e.g. add RT,RA,RB

847 # see http://bugs.libre-riscv.org/show_bug.cgi?id=282

848 asmop = yield from self.get_assembly_name()

849 print("call", name, asmop)

850

851 # check privileged

852 int_op = yield self.dec2.dec.op.internal_op

853 spr_msb = yield from self.get_spr_msb()

854

855 instr_is_privileged = False

856 if int_op in [MicrOp.OP_ATTN.value,

857 MicrOp.OP_MFMSR.value,

858 MicrOp.OP_MTMSR.value,

859 MicrOp.OP_MTMSRD.value,

860 # TODO: OP_TLBIE

861 MicrOp.OP_RFID.value]:

862 instr_is_privileged = True

863 if int_op in [MicrOp.OP_MFSPR.value,

864 MicrOp.OP_MTSPR.value] and spr_msb:

865 instr_is_privileged = True

866

867 print("is priv", instr_is_privileged, hex(self.msr.value),

868 self.msr[MSRb.PR])

869 # check MSR priv bit and whether op is privileged: if so, throw trap

870 if instr_is_privileged and self.msr[MSRb.PR] == 1:

871 self.TRAP(0x700, PIb.PRIV)

872 self.namespace['NIA'] = self.trap_nia

873 self.pc.update(self.namespace, self.is_svp64_mode)

874 return

875

876 # check halted condition

877 if name == 'attn':

878 self.halted = True

879 return

880

881 # check illegal instruction

882 illegal = False

883 if name not in ['mtcrf', 'mtocrf']:

884 illegal = name != asmop

885

886 # sigh deal with setvl not being supported by binutils (.long)

887 if asmop.startswith('setvl'):

888 illegal = False

889 name = 'setvl'

890

891 if illegal:

892 print("illegal", name, asmop)

893 self.TRAP(0x700, PIb.ILLEG)

894 self.namespace['NIA'] = self.trap_nia

895 self.pc.update(self.namespace, self.is_svp64_mode)

896 print("name %s != %s - calling ILLEGAL trap, PC: %x" %

897 (name, asmop, self.pc.CIA.value))

898 return

899

900 info = self.instrs[name]

901 yield from self.prep_namespace(info.form, info.op_fields)

902

903 # preserve order of register names

904 input_names = create_args(list(info.read_regs) +

905 list(info.uninit_regs))

906 print(input_names)

907

908 # get SVP64 entry for the current instruction

909 sv_rm = self.svp64rm.instrs.get(name)

910 if sv_rm is not None:

911 dest_cr, src_cr, src_byname, dest_byname = decode_extra(sv_rm)

912 else:

913 dest_cr, src_cr, src_byname, dest_byname = False, False, {}, {}

914 print ("sv rm", sv_rm, dest_cr, src_cr, src_byname, dest_byname)

915

916 # get SVSTATE VL (oh and print out some debug stuff)

917 if self.is_svp64_mode:

918 vl = self.svstate.vl.asint(msb0=True)

919 srcstep = self.svstate.srcstep.asint(msb0=True)

920 dststep = self.svstate.dststep.asint(msb0=True)

921 sv_a_nz = yield self.dec2.sv_a_nz

922 in1 = yield self.dec2.e.read_reg1.data

923 print ("SVP64: VL, srcstep, dststep, sv_a_nz, in1",

924 vl, srcstep, dststep, sv_a_nz, in1)

925

926 # get predicate mask

927 srcmask = dstmask = 0xffff_ffff_ffff_ffff

928 if self.is_svp64_mode:

929 pmode = yield self.dec2.rm_dec.predmode

930 sv_ptype = yield self.dec2.dec.op.SV_Ptype

931 srcpred = yield self.dec2.rm_dec.srcpred

932 dstpred = yield self.dec2.rm_dec.dstpred

933 pred_src_zero = yield self.dec2.rm_dec.pred_sz

934 pred_dst_zero = yield self.dec2.rm_dec.pred_dz

935 if pmode == SVP64PredMode.INT.value:

936 srcmask = dstmask = get_predint(self.gpr, dstpred)

937 if sv_ptype == SVPtype.P2.value:

938 srcmask = get_predint(self.gpr, srcpred)

939 elif pmode == SVP64PredMode.CR.value:

940 srcmask = dstmask = get_predcr(self.crl, dstpred, vl)

941 if sv_ptype == SVPtype.P2.value:

942 srcmask = get_predcr(self.crl, srcpred, vl)

943 print (" pmode", pmode)

944 print (" ptype", sv_ptype)

945 print (" srcpred", bin(srcpred))

946 print (" dstpred", bin(dstpred))

947 print (" srcmask", bin(srcmask))

948 print (" dstmask", bin(dstmask))

949 print (" pred_sz", bin(pred_src_zero))

950 print (" pred_dz", bin(pred_dst_zero))

951

952 # okaaay, so here we simply advance srcstep (TODO dststep)

953 # until the predicate mask has a "1" bit... or we run out of VL

954 # let srcstep==VL be the indicator to move to next instruction

955 if not pred_src_zero:

956 while (((1<<srcstep) & srcmask) == 0) and (srcstep != vl):

957 print (" skip", bin(1<<srcstep))

958 srcstep += 1

959 # same for dststep

960 if not pred_dst_zero:

961 while (((1<<dststep) & dstmask) == 0) and (dststep != vl):

962 print (" skip", bin(1<<dststep))

963 dststep += 1

964

965 # now work out if the relevant mask bits require zeroing

966 if pred_dst_zero:

967 pred_dst_zero = ((1<<dststep) & dstmask) == 0

968 if pred_src_zero:

969 pred_src_zero = ((1<<srcstep) & srcmask) == 0

970

971 # update SVSTATE with new srcstep

972 self.svstate.srcstep[0:7] = srcstep

973 self.svstate.dststep[0:7] = dststep

974 self.namespace['SVSTATE'] = self.svstate.spr

975 yield self.dec2.state.svstate.eq(self.svstate.spr.value)

976 yield Settle() # let decoder update

977 srcstep = self.svstate.srcstep.asint(msb0=True)

978 dststep = self.svstate.dststep.asint(msb0=True)

979 print (" srcstep", srcstep)

980 print (" dststep", dststep)

981

982 # check if end reached (we let srcstep overrun, above)

983 # nothing needs doing (TODO zeroing): just do next instruction

984 if srcstep == vl or dststep == vl:

985 self.svp64_reset_loop()

986 self.update_pc_next()

987 return

988

989 # VL=0 in SVP64 mode means "do nothing: skip instruction"

990 if self.is_svp64_mode and vl == 0:

991 self.pc.update(self.namespace, self.is_svp64_mode)

992 print("SVP64: VL=0, end of call", self.namespace['CIA'],

993 self.namespace['NIA'])

994 return

995

996 # main input registers (RT, RA ...)

997 inputs = []

998 for name in input_names:

999 # using PowerDecoder2, first, find the decoder index.

1000 # (mapping name RA RB RC RS to in1, in2, in3)

1001 regnum, is_vec = yield from get_pdecode_idx_in(self.dec2, name)

1002 if regnum is None:

1003 # doing this is not part of svp64, it's because output

1004 # registers, to be modified, need to be in the namespace.

1005 regnum, is_vec = yield from get_pdecode_idx_out(self.dec2, name)

1006

1007 # in case getting the register number is needed, _RA, _RB

1008 regname = "_" + name

1009 self.namespace[regname] = regnum

1010 if not self.is_svp64_mode or not pred_src_zero:

1011 print('reading reg %s %s' % (name, str(regnum)), is_vec)

1012 reg_val = self.gpr(regnum)

1013 else:

1014 print('zero input reg %s %s' % (name, str(regnum)), is_vec)

1015 reg_val = 0

1016 inputs.append(reg_val)

1017

1018 # "special" registers

1019 for special in info.special_regs:

1020 if special in special_sprs:

1021 inputs.append(self.spr[special])

1022 else:

1023 inputs.append(self.namespace[special])

1024

1025 # clear trap (trap) NIA

1026 self.trap_nia = None

1027

1028 # execute actual instruction here

1029 print("inputs", inputs)

1030 results = info.func(self, *inputs)

1031 print("results", results)

1032

1033 # "inject" decorator takes namespace from function locals: we need to

1034 # overwrite NIA being overwritten (sigh)

1035 if self.trap_nia is not None:

1036 self.namespace['NIA'] = self.trap_nia

1037

1038 print("after func", self.namespace['CIA'], self.namespace['NIA'])

1039

1040 # detect if CA/CA32 already in outputs (sra*, basically)

1041 already_done = 0

1042 if info.write_regs:

1043 output_names = create_args(info.write_regs)

1044 for name in output_names:

1045 if name == 'CA':

1046 already_done |= 1

1047 if name == 'CA32':

1048 already_done |= 2

1049

1050 print("carry already done?", bin(already_done))

1051 if hasattr(self.dec2.e.do, "output_carry"):

1052 carry_en = yield self.dec2.e.do.output_carry

1053 else:

1054 carry_en = False

1055 if carry_en:

1056 yield from self.handle_carry_(inputs, results, already_done)

1057

1058 if not self.is_svp64_mode: # yeah just no. not in parallel processing

1059 # detect if overflow was in return result

1060 overflow = None

1061 if info.write_regs:

1062 for name, output in zip(output_names, results):

1063 if name == 'overflow':

1064 overflow = output

1065

1066 if hasattr(self.dec2.e.do, "oe"):

1067 ov_en = yield self.dec2.e.do.oe.oe

1068 ov_ok = yield self.dec2.e.do.oe.ok

1069 else:

1070 ov_en = False

1071 ov_ok = False

1072 print("internal overflow", overflow, ov_en, ov_ok)

1073 if ov_en & ov_ok:

1074 yield from self.handle_overflow(inputs, results, overflow)

1075

1076 # only do SVP64 dest predicated Rc=1 if dest-pred is not enabled

1077 rc_en = False

1078 if not self.is_svp64_mode or not pred_dst_zero:

1079 if hasattr(self.dec2.e.do, "rc"):

1080 rc_en = yield self.dec2.e.do.rc.rc

1081 if rc_en:

1082 regnum, is_vec = yield from get_pdecode_cr_out(self.dec2, "CR0")

1083 self.handle_comparison(results, regnum)

1084

1085 # any modified return results?

1086 if info.write_regs:

1087 for name, output in zip(output_names, results):

1088 if name == 'overflow': # ignore, done already (above)

1089 continue

1090 if isinstance(output, int):

1091 output = SelectableInt(output, 256)

1092 if name in ['CA', 'CA32']:

1093 if carry_en:

1094 print("writing %s to XER" % name, output)

1095 self.spr['XER'][XER_bits[name]] = output.value

1096 else:

1097 print("NOT writing %s to XER" % name, output)

1098 elif name in info.special_regs:

1099 print('writing special %s' % name, output, special_sprs)

1100 if name in special_sprs:

1101 self.spr[name] = output

1102 else:

1103 self.namespace[name].eq(output)

1104 if name == 'MSR':

1105 print('msr written', hex(self.msr.value))

1106 else:

1107 regnum, is_vec = yield from get_pdecode_idx_out(self.dec2,

1108 name)

1109 if regnum is None:

1110 # temporary hack for not having 2nd output

1111 regnum = yield getattr(self.decoder, name)

1112 is_vec = False

1113 if self.is_svp64_mode and pred_dst_zero:

1114 print('zeroing reg %d %s' % (regnum, str(output)),

1115 is_vec)

1116 output = SelectableInt(0, 256)

1117 else:

1118 print('writing reg %d %s' % (regnum, str(output)),

1119 is_vec)

1120 if output.bits > 64:

1121 output = SelectableInt(output.value, 64)

1122 self.gpr[regnum] = output

1123

1124 # check if it is the SVSTATE.src/dest step that needs incrementing

1125 # this is our Sub-Program-Counter loop from 0 to VL-1

1126 if self.is_svp64_mode:

1127 # XXX twin predication TODO

1128 vl = self.svstate.vl.asint(msb0=True)

1129 mvl = self.svstate.maxvl.asint(msb0=True)

1130 srcstep = self.svstate.srcstep.asint(msb0=True)

1131 dststep = self.svstate.dststep.asint(msb0=True)

1132 sv_ptype = yield self.dec2.dec.op.SV_Ptype

1133 no_out_vec = not (yield self.dec2.no_out_vec)

1134 no_in_vec = not (yield self.dec2.no_in_vec)

1135 print (" svstate.vl", vl)

1136 print (" svstate.mvl", mvl)

1137 print (" svstate.srcstep", srcstep)

1138 print (" svstate.dststep", dststep)

1139 print (" no_out_vec", no_out_vec)

1140 print (" no_in_vec", no_in_vec)

1141 print (" sv_ptype", sv_ptype, sv_ptype == SVPtype.P2.value)

1142 # check if srcstep needs incrementing by one, stop PC advancing

1143 # svp64 loop can end early if the dest is scalar for single-pred

1144 # but for 2-pred both src/dest have to be checked.

1145 # XXX this might not be true! it may just be LD/ST

1146 if sv_ptype == SVPtype.P2.value:

1147 svp64_is_vector = (no_out_vec or no_in_vec)

1148 else:

1149 svp64_is_vector = no_out_vec

1150 if svp64_is_vector and srcstep != vl-1 and dststep != vl-1:

1151 self.svstate.srcstep += SelectableInt(1, 7)

1152 self.svstate.dststep += SelectableInt(1, 7)

1153 self.pc.NIA.value = self.pc.CIA.value

1154 self.namespace['NIA'] = self.pc.NIA

1155 self.namespace['SVSTATE'] = self.svstate.spr

1156 print("end of sub-pc call", self.namespace['CIA'],

1157 self.namespace['NIA'])

1158 return # DO NOT allow PC to update whilst Sub-PC loop running

1159 # reset loop to zero

1160 self.svp64_reset_loop()

1161

1162 self.update_pc_next()

1163

1164 def update_pc_next(self):

1165 # UPDATE program counter

1166 self.pc.update(self.namespace, self.is_svp64_mode)

1167 self.svstate.spr = self.namespace['SVSTATE']

1168 print("end of call", self.namespace['CIA'],

1169 self.namespace['NIA'],

1170 self.namespace['SVSTATE'])

1171

1172 def svp64_reset_loop(self):

1173 self.svstate.srcstep[0:7] = 0

1174 self.svstate.dststep[0:7] = 0

1175 print (" svstate.srcstep loop end (PC to update)")

1176 self.pc.update_nia(self.is_svp64_mode)

1177 self.namespace['NIA'] = self.pc.NIA

1178 self.namespace['SVSTATE'] = self.svstate.spr

1179

1180 def inject():

1181 """Decorator factory.

1182

1183 this decorator will "inject" variables into the function's namespace,

1184 from the *dictionary* in self.namespace. it therefore becomes possible

1185 to make it look like a whole stack of variables which would otherwise

1186 need "self." inserted in front of them (*and* for those variables to be

1187 added to the instance) "appear" in the function.

1188

1189 "self.namespace['SI']" for example becomes accessible as just "SI" but

1190 *only* inside the function, when decorated.

1191 """

1192 def variable_injector(func):

1193 @wraps(func)

1194 def decorator(*args, **kwargs):

1195 try:

1196 func_globals = func.__globals__ # Python 2.6+

1197 except AttributeError:

1198 func_globals = func.func_globals # Earlier versions.

1199

1200 context = args[0].namespace # variables to be injected

1201 saved_values = func_globals.copy() # Shallow copy of dict.

1202 func_globals.update(context)

1203 result = func(*args, **kwargs)

1204 print("globals after", func_globals['CIA'], func_globals['NIA'])

1205 print("args[0]", args[0].namespace['CIA'],

1206 args[0].namespace['NIA'],

1207 args[0].namespace['SVSTATE'])

1208 args[0].namespace = func_globals

1209 #exec (func.__code__, func_globals)

1210

1211 # finally:

1212 # func_globals = saved_values # Undo changes.

1213

1214 return result

1215

1216 return decorator

1217

1218 return variable_injector

1219

1220