mem-ruby: Hit latencies defined by the controllers
authorTiago Muck <tiago.muck@arm.com>
Tue, 19 Feb 2019 21:58:33 +0000 (15:58 -0600)
committerTiago Mück <tiago.muck@arm.com>
Tue, 14 May 2019 22:01:12 +0000 (22:01 +0000)
commit496d5ed3e1f7dad42b0c2ebe0050d84621be8f99
tree0ec4954d60e37d1bfe595aa6b1c7a6913a27f005
parent42e55cdafdac41830839ac2584d99a8dd5e3d95e
mem-ruby: Hit latencies defined by the controllers

Removed the icache/dcache hit latency parameters from the Sequencer.
They were replaced by the mandatory queue enqueue latency that is now
defined by the top-level cache controller. By default, the latency is
defined by the mandatory_queue_latency parameter. When the latency
depends on specific protocol states or on the request type, the protocol
may override the mandatoryQueueLatency function.

Change-Id: I72e57a7ea49501ef81dc7f591bef14134274647c
Signed-off-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18413
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
configs/ruby/GPU_RfO.py
configs/ruby/MOESI_AMD_Base.py
src/mem/ruby/slicc_interface/AbstractController.cc
src/mem/ruby/slicc_interface/AbstractController.hh
src/mem/ruby/slicc_interface/Controller.py
src/mem/ruby/system/GPUCoalescer.cc
src/mem/ruby/system/GPUCoalescer.hh
src/mem/ruby/system/GPUCoalescer.py
src/mem/ruby/system/Sequencer.cc
src/mem/ruby/system/Sequencer.py