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(parent: 0835a86) | patch
Fix integer signing grammar
authorLukasz Dalek <ldalek@antmicro.com>
Mon, 18 May 2020 19:01:16 +0000 (21:01 +0200)
committerKamil Rakoczy <krakoczy@antmicro.com>
Fri, 26 Jun 2020 13:35:56 +0000 (15:35 +0200)
commit7cb56f34b06de666935fbda315ce7c7bd45048b3
tree2f5d565b0cbbc530dae7cb44c738a4217285e60ctree
parent0835a86e30fc2a934f5e6c96b28c90b59654ed92commit | diff
Fix integer signing grammar

This commit fixes signed/unsigned grammar in parameters as defined in SV
LRM A2.2.1. Example of correct parameters:

parameter integer signed i = 0;
parameter integer unsigned i = 0;

Example of incorrect parameters:

parameter signed integer i = 0;
parameter unsigned integer i = 0;

Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
frontends/verilog/verilog_parser.y diff | blob | history