Support logic typed parameters
authorLukasz Dalek <ldalek@antmicro.com>
Mon, 18 May 2020 19:02:19 +0000 (21:02 +0200)
committerKamil Rakoczy <krakoczy@antmicro.com>
Mon, 6 Jul 2020 07:18:48 +0000 (09:18 +0200)
commit7e83a51fc96495c558a31fc3ca6c1a5ba4764f15
treee818a19b9511ff93a660c813b1bc371891bd13ad
parent09ecb9b2cf3ab76841d30712bf70dafc6d47ef67
Support logic typed parameters

Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
frontends/verilog/verilog_parser.y