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(parent: 45a4747) | patch
back.rtlil: do not translate empty fragments.
authorwhitequark <whitequark@whitequark.org>
Sun, 23 Dec 2018 09:20:02 +0000 (09:20 +0000)
committerwhitequark <whitequark@whitequark.org>
Sun, 23 Dec 2018 09:20:02 +0000 (09:20 +0000)
commit9faa1d37425ddafb5b2e76d502d86e3bff9ae54c
tree556b6b3e3a9e8f77890adaa82b671f0b8ab8a485tree
parent45a474788cbaed361b4ad8c31aed607da28f1d14commit | diff
back.rtlil: do not translate empty fragments.

The resulting Verilog confuses some frontends.
nmigen/back/rtlil.py diff | blob | history