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(parent: 5a7b4c3) | patch
gen/fhdl/verilog: allow single element verilog inline attribute
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 28 Aug 2019 03:15:45 +0000 (05:15 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 28 Aug 2019 03:24:11 +0000 (05:24 +0200)
commitb845755995a8517d8e0ffa86156fb5577201f7d4
tree705ef51a455e9a447212ce605af9d883252393f3tree
parent5a7b4c3406fc080e780b76a0324ded5ac9721f71commit | diff
gen/fhdl/verilog: allow single element verilog inline attribute
litex/build/lattice/diamond.py diff | blob | history
litex/gen/fhdl/verilog.py diff | blob | history