x86: correct handling of LAR and LSL
authorJan Beulich <jbeulich@suse.com>
Thu, 24 Nov 2022 08:34:52 +0000 (09:34 +0100)
committerJan Beulich <jbeulich@suse.com>
Thu, 24 Nov 2022 08:34:52 +0000 (09:34 +0100)
commitc9f5b96bdab031e9520d98e01ee1bef1ffd3b961
tree7bf77e81e28c7d8fda786174240f22c2166d057c
parentbde9f9d7e978b190ff6fc7207e2fe293d7c989a7
x86: correct handling of LAR and LSL

Both uniformly only ever take 16-bit memory operands while at the same
time requiring matching (in size) register operands, which then also
should disassemble that way. This in particular requires splitting each
of the templates for the assembler and separating decode of the
register and memory forms in the disassembler.
gas/config/tc-i386-intel.c
gas/testsuite/gas/i386/intel-intel.d
gas/testsuite/gas/i386/intel.d
gas/testsuite/gas/i386/intel.s
gas/testsuite/gas/i386/intelbad.l
gas/testsuite/gas/i386/intelbad.s
opcodes/i386-dis.c
opcodes/i386-opc.tbl
opcodes/i386-tbl.h