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(parent: b5a9909) | patch
fhdl/verilog: do not use initial begin in _printinit (not accepted by all synthesis...
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 16 Mar 2015 22:39:32 +0000 (23:39 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 16 Mar 2015 22:47:07 +0000 (23:47 +0100)
commite946f6e4538277308e374cd1f0b1b9a31f66dc5a
treed30b8011f571d28270c1a36ad1d7568b6c2d3cb4tree
parentb5a9909b089933c230f6d0ce24c18f153a345cdfcommit | diff
fhdl/verilog: do not use initial begin in _printinit (not accepted by all synthesis tools ex: Synplify Pro does not accept it)
migen/fhdl/verilog.py diff | blob | history