From 068860a780b09912781631eb34d0b9d07d4501ff Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 8 Jul 2020 17:41:48 +0100 Subject: [PATCH] stashing current state of investigation whilst looking for regression bug --- src/soc/decoder/isa/caller.py | 2 ++ src/soc/simple/test/test_issuer.py | 32 ++++++++++++++++-------------- 2 files changed, 19 insertions(+), 15 deletions(-) diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index 133d4b09..e2e97edb 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -490,6 +490,7 @@ class ISACaller: # TODO, asmregs is from the spec, e.g. add RT,RA,RB # see http://bugs.libre-riscv.org/show_bug.cgi?id=282 asmcode = yield self.dec2.dec.op.asmcode + print ("get assembly name asmcode", asmcode) asmop = insns.get(asmcode, None) # sigh reconstruct the assembly instruction name @@ -524,6 +525,7 @@ class ISACaller: return asmop def call(self, name): + name = name.strip() # remove spaces if not already done so if self.halted: print ("halted - not executing", name) return diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py index e0c404fa..40592061 100644 --- a/src/soc/simple/test/test_issuer.py +++ b/src/soc/simple/test/test_issuer.py @@ -26,13 +26,14 @@ from soc.fu.compunits.test.test_compunit import (setup_test_memory, # test with ALU data and Logical data from soc.fu.alu.test.test_pipe_caller import ALUTestCase -from soc.fu.logical.test.test_pipe_caller import LogicalTestCase -from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase -from soc.fu.cr.test.test_pipe_caller import CRTestCase -from soc.fu.branch.test.test_pipe_caller import BranchTestCase -from soc.fu.spr.test.test_pipe_caller import SPRTestCase -from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase -from soc.simulator.test_sim import (GeneralTestCases, AttnTestCase) +#from soc.fu.logical.test.test_pipe_caller import LogicalTestCase +#from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase +#from soc.fu.cr.test.test_pipe_caller import CRTestCase +#from soc.fu.branch.test.test_pipe_caller import BranchTestCase +#from soc.fu.spr.test.test_pipe_caller import SPRTestCase +#from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase +#from soc.simulator.test_sim import (GeneralTestCases, AttnTestCase) +#from soc.simulator.test_helloworld_sim import HelloTestCases def setup_i_memory(imem, startaddr, instructions): @@ -178,15 +179,16 @@ class TestRunner(FHDLTestCase): if __name__ == "__main__": unittest.main(exit=False) suite = unittest.TestSuite() - suite.addTest(TestRunner(AttnTestCase.test_data)) - suite.addTest(TestRunner(GeneralTestCases.test_data)) - suite.addTest(TestRunner(LDSTTestCase.test_data)) - suite.addTest(TestRunner(CRTestCase.test_data)) - suite.addTest(TestRunner(ShiftRotTestCase.test_data)) - suite.addTest(TestRunner(LogicalTestCase.test_data)) + #suite.addTest(TestRunner(HelloTestCases.test_data)) + #suite.addTest(TestRunner(AttnTestCase.test_data)) + #suite.addTest(TestRunner(GeneralTestCases.test_data)) + #suite.addTest(TestRunner(LDSTTestCase.test_data)) + #suite.addTest(TestRunner(CRTestCase.test_data)) + #suite.addTest(TestRunner(ShiftRotTestCase.test_data)) + #suite.addTest(TestRunner(LogicalTestCase.test_data)) suite.addTest(TestRunner(ALUTestCase.test_data)) - suite.addTest(TestRunner(BranchTestCase.test_data)) - suite.addTest(TestRunner(SPRTestCase.test_data)) + #suite.addTest(TestRunner(BranchTestCase.test_data)) + #suite.addTest(TestRunner(SPRTestCase.test_data)) runner = unittest.TextTestRunner() runner.run(suite) -- 2.30.2