From 444ab8126d38bfb236b272226f0a57dafd0ac6de Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Mon, 10 Apr 2017 23:08:23 -0700 Subject: [PATCH] i965/drm: Make stride/pitch a uint32_t. struct drm_i915_gem_set_tiling's stride field is a __u32. intel_mipmap_tree::stride is a uint32_t. Using unsigned long just doesn't make sense. Switching also lets us drop many pointless locals that only existed to deal with the type mismatch. Reviewed-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_bufmgr.c | 11 ++++---- src/mesa/drivers/dri/i965/brw_bufmgr.h | 4 +-- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 26 +++++-------------- src/mesa/drivers/dri/i965/intel_screen.c | 8 +++--- 4 files changed, 18 insertions(+), 31 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c b/src/mesa/drivers/dri/i965/brw_bufmgr.c index 5eb9f57f7b6..3dcd10b21f3 100644 --- a/src/mesa/drivers/dri/i965/brw_bufmgr.c +++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c @@ -152,8 +152,8 @@ bo_tile_size(struct brw_bufmgr *bufmgr, unsigned long size, uint32_t tiling) * given chip. We use 512 as the minimum to allow for a later tiling * change. */ -static unsigned long -bo_tile_pitch(struct brw_bufmgr *bufmgr, unsigned long pitch, uint32_t tiling) +static uint32_t +bo_tile_pitch(struct brw_bufmgr *bufmgr, uint32_t pitch, uint32_t tiling) { unsigned long tile_width; @@ -247,7 +247,7 @@ bo_alloc_internal(struct brw_bufmgr *bufmgr, unsigned long size, unsigned long flags, uint32_t tiling_mode, - unsigned long stride, unsigned int alignment) + uint32_t stride, unsigned int alignment) { struct brw_bo *bo; unsigned int page_size = getpagesize(); @@ -377,9 +377,10 @@ brw_bo_alloc(struct brw_bufmgr *bufmgr, struct brw_bo * brw_bo_alloc_tiled(struct brw_bufmgr *bufmgr, const char *name, int x, int y, int cpp, uint32_t tiling, - unsigned long *pitch, unsigned long flags) + uint32_t *pitch, unsigned long flags) { - unsigned long size, stride; + unsigned long size; + uint32_t stride; unsigned long aligned_y, height_alignment; /* If we're tiled, our allocations are in 8 or 32-row blocks, diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h b/src/mesa/drivers/dri/i965/brw_bufmgr.h index 2c221850afc..93a929d20e3 100644 --- a/src/mesa/drivers/dri/i965/brw_bufmgr.h +++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h @@ -109,7 +109,7 @@ struct brw_bo { */ uint32_t tiling_mode; uint32_t swizzle_mode; - unsigned long stride; + uint32_t stride; time_t free_time; @@ -161,7 +161,7 @@ struct brw_bo *brw_bo_alloc_tiled(struct brw_bufmgr *bufmgr, const char *name, int x, int y, int cpp, uint32_t tiling_mode, - unsigned long *pitch, + uint32_t *pitch, unsigned long flags); /** Takes a reference on a buffer object */ diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 137bb075f6a..db0a3975279 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -611,7 +611,6 @@ miptree_create(struct brw_context *brw, if (layout_flags & MIPTREE_LAYOUT_ACCELERATED_UPLOAD) alloc_flags |= BO_ALLOC_FOR_RENDER; - unsigned long pitch; mt->etc_format = etc_format; if (format == MESA_FORMAT_S_UINT8) { @@ -619,17 +618,15 @@ miptree_create(struct brw_context *brw, mt->bo = brw_bo_alloc_tiled(brw->bufmgr, "miptree", ALIGN(mt->total_width, 64), ALIGN(mt->total_height, 64), - mt->cpp, mt->tiling, &pitch, + mt->cpp, mt->tiling, &mt->pitch, alloc_flags); } else { mt->bo = brw_bo_alloc_tiled(brw->bufmgr, "miptree", mt->total_width, mt->total_height, - mt->cpp, mt->tiling, &pitch, + mt->cpp, mt->tiling, &mt->pitch, alloc_flags); } - mt->pitch = pitch; - return mt; } @@ -657,7 +654,6 @@ intel_miptree_create(struct brw_context *brw, */ if (brw->gen < 6 && mt->bo->size >= brw->max_gtt_map_object_size && mt->tiling == I915_TILING_Y) { - unsigned long pitch = mt->pitch; const uint32_t alloc_flags = (layout_flags & MIPTREE_LAYOUT_ACCELERATED_UPLOAD) ? BO_ALLOC_FOR_RENDER : 0; @@ -668,8 +664,7 @@ intel_miptree_create(struct brw_context *brw, brw_bo_unreference(mt->bo); mt->bo = brw_bo_alloc_tiled(brw->bufmgr, "miptree", mt->total_width, mt->total_height, mt->cpp, - mt->tiling, &pitch, alloc_flags); - mt->pitch = pitch; + mt->tiling, &mt->pitch, alloc_flags); } mt->offset = 0; @@ -1544,7 +1539,6 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw, */ const uint32_t alloc_flags = is_lossless_compressed ? 0 : BO_ALLOC_FOR_RENDER; - unsigned long pitch; /* ISL has stricter set of alignment rules then the drm allocator. * Therefore one can pass the ISL dimensions in terms of bytes instead of @@ -1552,10 +1546,8 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw, */ buf->bo = brw_bo_alloc_tiled(brw->bufmgr, "ccs-miptree", buf->pitch, buf->size / buf->pitch, - 1, I915_TILING_Y, &pitch, alloc_flags); - if (buf->bo) { - assert(pitch == buf->pitch); - } else { + 1, I915_TILING_Y, &buf->pitch, alloc_flags); + if (!buf->bo) { free(buf); return false; } @@ -1684,10 +1676,9 @@ intel_gen7_hiz_buf_create(struct brw_context *brw, hz_height = DIV_ROUND_UP(hz_qpitch * Z0, 2 * 8) * 8; } - unsigned long pitch; buf->aux_base.bo = brw_bo_alloc_tiled(brw->bufmgr, "hiz", hz_width, hz_height, 1, - I915_TILING_Y, &pitch, + I915_TILING_Y, &buf->aux_base.pitch, BO_ALLOC_FOR_RENDER); if (!buf->aux_base.bo) { free(buf); @@ -1695,7 +1686,6 @@ intel_gen7_hiz_buf_create(struct brw_context *brw, } buf->aux_base.size = hz_width * hz_height; - buf->aux_base.pitch = pitch; return buf; } @@ -1776,10 +1766,9 @@ intel_gen8_hiz_buf_create(struct brw_context *brw, hz_height = DIV_ROUND_UP(buf->aux_base.qpitch, 2 * 8) * 8 * Z0; } - unsigned long pitch; buf->aux_base.bo = brw_bo_alloc_tiled(brw->bufmgr, "hiz", hz_width, hz_height, 1, - I915_TILING_Y, &pitch, + I915_TILING_Y, &buf->aux_base.pitch, BO_ALLOC_FOR_RENDER); if (!buf->aux_base.bo) { free(buf); @@ -1787,7 +1776,6 @@ intel_gen8_hiz_buf_create(struct brw_context *brw, } buf->aux_base.size = hz_width * hz_height; - buf->aux_base.pitch = pitch; return buf; } diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index f1e9d660d94..be5b195eb31 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -573,7 +573,6 @@ intel_create_image_common(__DRIscreen *dri_screen, */ uint32_t tiling = I915_TILING_X; int cpp; - unsigned long pitch; /* Callers of this may specify a modifier, or a dri usage, but not both. The * newer modifier interface deprecates the older usage flags newer modifier @@ -615,14 +614,13 @@ intel_create_image_common(__DRIscreen *dri_screen, cpp = _mesa_get_format_bytes(image->format); image->bo = brw_bo_alloc_tiled(screen->bufmgr, "image", width, height, cpp, tiling, - &pitch, 0); + &image->pitch, 0); if (image->bo == NULL) { free(image); return NULL; } image->width = width; image->height = height; - image->pitch = pitch; image->modifier = modifier; return image; @@ -1293,7 +1291,7 @@ intel_detect_swizzling(struct intel_screen *screen) { struct brw_bo *buffer; unsigned long flags = 0; - unsigned long aligned_pitch; + uint32_t aligned_pitch; uint32_t tiling = I915_TILING_X; uint32_t swizzle_mode = 0; @@ -2097,7 +2095,7 @@ intelAllocateBuffer(__DRIscreen *dri_screen, /* The front and back buffers are color buffers, which are X tiled. GEN9+ * supports Y tiled and compressed buffers, but there is no way to plumb that * through to here. */ - unsigned long pitch; + uint32_t pitch; int cpp = format / 8; intelBuffer->bo = brw_bo_alloc_tiled(screen->bufmgr, "intelAllocateBuffer", -- 2.30.2