From 573a8c95a4f7aa82478b788b429ae606634951bc Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 22 Aug 2019 02:41:44 +0100 Subject: [PATCH] reduce multiply sim delay by 1/10th, seems to "fix" test problem --- src/ieee754/part_mul_add/test/test_multiply.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/ieee754/part_mul_add/test/test_multiply.py b/src/ieee754/part_mul_add/test/test_multiply.py index 409d482f..e50f8cce 100644 --- a/src/ieee754/part_mul_add/test/test_multiply.py +++ b/src/ieee754/part_mul_add/test/test_multiply.py @@ -56,10 +56,10 @@ class TestPartitionPoints(unittest.TestCase): self.assertEqual((yield partition_points[1]), True) self.assertEqual((yield partition_points[5]), False) yield partition_point_10.eq(0) - yield Delay(1e-6) + yield Delay(0.1e-6) self.assertEqual((yield mask), 0xFFFD) yield partition_point_10.eq(1) - yield Delay(1e-6) + yield Delay(0.1e-6) self.assertEqual((yield mask), 0xFBFD) sim.add_process(async_process) @@ -94,7 +94,7 @@ class TestPartitionedAdder(unittest.TestCase): (0x0000, 0xFFFF)]: yield module.a.eq(a) yield module.b.eq(b) - yield Delay(1e-6) + yield Delay(0.1e-6) y = 0 for mask in mask_list: y |= mask & ((a & mask) + (b & mask)) @@ -154,7 +154,7 @@ class TestAddReduce(unittest.TestCase): if gen_or_check == GenOrCheck.Generate: for i, v in zip(inputs, values): yield i.eq(v) - yield Delay(1e-6) + yield Delay(0.1e-6) y = 0 for mask in mask_list: v = 0 @@ -459,7 +459,7 @@ class TestMul8_16_32_64(unittest.TestCase): yield module.a.eq(a) yield module.b.eq(b) output2, intermediate_output2 = self.simd_mul(a, b, lanes) - yield Delay(1e-6) + yield Delay(0.1e-6) if gen_or_check == GenOrCheck.Check: intermediate_output = (yield module.intermediate_output) self.assertEqual(intermediate_output, -- 2.30.2