From b30bf92e8851241db5375b249897a84ba62ccdef Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 25 Jun 2019 14:17:34 +0100 Subject: [PATCH] split out pred table format --- simple_v_extension/abridged_spec.mdwn | 28 +---------------------- simple_v_extension/pred_table_format.mdwn | 27 ++++++++++++++++++++++ simple_v_extension/specification.mdwn | 27 +--------------------- 3 files changed, 29 insertions(+), 53 deletions(-) create mode 100644 simple_v_extension/pred_table_format.mdwn diff --git a/simple_v_extension/abridged_spec.mdwn b/simple_v_extension/abridged_spec.mdwn index 65e0f373d..c54884dec 100644 --- a/simple_v_extension/abridged_spec.mdwn +++ b/simple_v_extension/abridged_spec.mdwn @@ -231,36 +231,10 @@ is an indirect lookup that allows the RV opcodes to not need modification. The handling of each (trap or conditional test) is slightly different: see Instruction sections for further details -16 bit format: - -| PrCSR | (15..11) | 10 | 9 | 8 | (7..1) | 0 | -| ----- | - | - | - | - | ------- | ------- | -| 0 | predidx | zero0 | inv0 | i/f | regidx | ffirst0 | -| 1 | predidx | zero1 | inv1 | i/f | regidx | ffirst1 | -| 2 | predidx | zero2 | inv2 | i/f | regidx | ffirst2 | -| 3 | predidx | zero3 | inv3 | i/f | regidx | ffirst3 | - -Note: predidx=x0, zero=1, inv=1 is a RESERVED encoding. Its use must -generate an illegal instruction trap. - -8 bit format: - -| PrCSR | 7 | 6 | 5 | (4..0) | -| ----- | - | - | - | ------- | -| 0 | zero0 | inv0 | i/f | regnum | - -Mapping from 8 to 16 bit format, the table becomes: - -| PrCSR | (15..11) | 10 | 9 | 8 | (7..1) | 0 | -| ----- | - | - | - | - | ------- | ------- | -| 0 | x9 | zero0 | inv0 | i/f | regnum | ff=0 | -| 1 | x10 | zero1 | inv1 | i/f | regnum | ff=0 | -| 2 | x11 | zero2 | inv2 | i/f | regnum | ff=0 | -| 3 | x12 | zero3 | inv3 | i/f | regnum | ff=0 | +[[!inline raw="yes" pages="simple_v_extension/pred_table_format" ]] Pseudocode for predication: - [[!inline raw="yes" pages="simple_v_extension/pred_table" ]] [[!inline raw="yes" pages="simple_v_extension/get_pred_value" ]] diff --git a/simple_v_extension/pred_table_format.mdwn b/simple_v_extension/pred_table_format.mdwn new file mode 100644 index 000000000..1339d728d --- /dev/null +++ b/simple_v_extension/pred_table_format.mdwn @@ -0,0 +1,27 @@ +16 bit format: + +| PrCSR | (15..11) | 10 | 9 | 8 | (7..1) | 0 | +| ----- | - | - | - | - | ------- | ------- | +| 0 | predidx | zero0 | inv0 | i/f | regidx | ffirst0 | +| 1 | predidx | zero1 | inv1 | i/f | regidx | ffirst1 | +| 2 | predidx | zero2 | inv2 | i/f | regidx | ffirst2 | +| 3 | predidx | zero3 | inv3 | i/f | regidx | ffirst3 | + +Note: predidx=x0, zero=1, inv=1 is a RESERVED encoding. Its use must +generate an illegal instruction trap. + +8 bit format: + +| PrCSR | 7 | 6 | 5 | (4..0) | +| ----- | - | - | - | ------- | +| 0 | zero0 | inv0 | i/f | regnum | + +Mapping from 8 to 16 bit format, the table becomes: + +| PrCSR | (15..11) | 10 | 9 | 8 | (7..1) | 0 | +| ----- | - | - | - | - | ------- | ------- | +| 0 | x9 | zero0 | inv0 | i/f | regnum | ff=0 | +| 1 | x10 | zero1 | inv1 | i/f | regnum | ff=0 | +| 2 | x11 | zero2 | inv2 | i/f | regnum | ff=0 | +| 3 | x12 | zero3 | inv3 | i/f | regnum | ff=0 | + diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index 81e65796e..53d9837af 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -597,23 +597,7 @@ in the instruction, due to the redirection through the lookup table. The handling of each (trap or conditional test) is slightly different: see Instruction sections for further details -16 bit format: - -| PrCSR | (15..11) | 10 | 9 | 8 | (7..1) | 0 | -| ----- | - | - | - | - | ------- | ------- | -| 0 | predidx | zero0 | inv0 | i/f | regidx | ffirst0 | -| 1 | predidx | zero1 | inv1 | i/f | regidx | ffirst1 | -| 2 | predidx | zero2 | inv2 | i/f | regidx | ffirst2 | -| 3 | predidx | zero3 | inv3 | i/f | regidx | ffirst3 | - -Note: predidx=x0, zero=1, inv=1 is a RESERVED encoding. Its use must -generate an illegal instruction trap. - -8 bit format: - -| PrCSR | 7 | 6 | 5 | (4..0) | -| ----- | - | - | - | ------- | -| 0 | zero0 | inv0 | i/f | regnum | +[[!inline raw="yes" pages="simple_v_extension/pred_table_format" ]] The 8 bit format is a compact and less expressive variant of the full 16 bit format. Using the 8 bit formatis very different: the predicate @@ -621,15 +605,6 @@ register to use is implicit, and numbering begins inplicitly from x9. The regnum is still used to "activate" predication, in the same fashion as described above. -Thus if we map from 8 to 16 bit format, the table becomes: - -| PrCSR | (15..11) | 10 | 9 | 8 | (7..1) | 0 | -| ----- | - | - | - | - | ------- | ------- | -| 0 | x9 | zero0 | inv0 | i/f | regnum | ff=0 | -| 1 | x10 | zero1 | inv1 | i/f | regnum | ff=0 | -| 2 | x11 | zero2 | inv2 | i/f | regnum | ff=0 | -| 3 | x12 | zero3 | inv3 | i/f | regnum | ff=0 | - The 16 bit Predication CSR Table is a key-value store, so implementation-wise it will be faster to turn the table around (maintain topologically equivalent state): -- 2.30.2