From 981b30b1333762d982a90c28432ffde07d8c6645 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 9 Dec 2021 15:06:07 +0000 Subject: [PATCH] make icache accessible to core, working back to TestIssuer --- src/soc/simple/core.py | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index 428b19f2..f80ed141 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -147,13 +147,16 @@ class NonProductionCore(ControlBase): # only include mmu if enabled in pspec self.fus = AllFunctionUnits(pspec, pilist=[pi]) - # link LoadStore1 into MMU + # link LoadStore1 into MMU and make L1 I-Cache easy to get at mmu = self.fus.get_fu('mmu0') + ldst0 = self.fus.get_fu('ldst0') print ("core pspec", pspec.ldst_ifacetype) print ("core mmu", mmu) if mmu is not None: - print ("core lsmem.lsi", l0.cmpi.lsmem.lsi) - mmu.alu.set_ldst_interface(l0.cmpi.lsmem.lsi) + lsi = l0.cmpi.lsmem.lsi # a LoadStore1 Interface object + print ("core lsmem.lsi", lsi) + mmu.alu.set_ldst_interface(lsi) + self.icache = lsi.icache # register files (yes plural) self.regs = RegFiles(pspec, make_hazard_vecs=self.make_hazard_vecs) -- 2.30.2