From e409f31f74623ebbf3c53f50388541b7319e0937 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 8 Nov 2021 14:14:43 +0000 Subject: [PATCH] use p.i_valid in core instead of explicit signal ivalid_i converting core to Pipeline API --- src/soc/simple/core.py | 5 +++-- src/soc/simple/issuer.py | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index a0c4a816..a36fc92a 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -91,7 +91,6 @@ class CoreInput: self.sv_pred_dm = Signal() # TODO: SIMD width # issue/valid/busy signalling - self.ivalid_i = Signal(reset_less=True) # instruction is valid self.issue_i = Signal(reset_less=True) def eq(self, i): @@ -100,6 +99,7 @@ class CoreInput: self.state.eq(i.state) self.raw_insn_i.eq(i.raw_insn_i) self.bigendian_i.eq(i.bigendian_i) + self.issue_i.eq(i.issue_i) if not self.svp64_en: return self.sv_rm.eq(i.sv_rm) @@ -277,12 +277,13 @@ class NonProductionCore(ControlBase): sync += counter.eq(counter - 1) comb += busy_o.eq(1) - with m.If(self.i.ivalid_i): # run only when valid + with m.If(self.p.i_valid): # run only when valid with m.Switch(self.i.e.do.insn_type): # check for ATTN: halt if true with m.Case(MicrOp.OP_ATTN): m.d.sync += self.o.core_terminate_o.eq(1) + # fake NOP - this isn't really used (Issuer detects NOP) with m.Case(MicrOp.OP_NOP): sync += counter.eq(2) comb += busy_o.eq(1) diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index d208e1c2..e917756e 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -867,7 +867,7 @@ class TestIssuerInternal(Elaboratable): # temporaries core_busy_o = ~core.p.o_ready # core is busy - core_ivalid_i = core.i.ivalid_i # instruction is valid + core_ivalid_i = core.p.i_valid # instruction is valid core_issue_i = core.i.issue_i # instruction is issued insn_type = core.i.e.do.insn_type # instruction MicroOp type -- 2.30.2