From 3ba07d7528444bc085778bc7f643352e866f7a88 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 23 Apr 2021 15:30:39 +0100 Subject: [PATCH] move over to from openpower imports --- src/soc/debug/firmware_upload.py | 2 +- src/soc/decoder/formal/proof_decoder.py | 6 +++--- src/soc/decoder/formal/proof_decoder2.py | 6 +++--- src/soc/decoder/helpers.py | 8 ++++---- src/soc/decoder/isa/caller.py | 16 ++++++++-------- src/soc/decoder/power_pseudo.py | 10 +++++----- src/soc/decoder/power_regspec_map.py | 2 +- src/soc/decoder/power_svp64.py | 2 +- src/soc/decoder/power_svp64_extra.py | 2 +- src/soc/decoder/power_svp64_rm.py | 2 +- src/soc/decoder/pseudo/lexer.py | 2 +- src/soc/decoder/pseudo/parser.py | 6 +++--- src/soc/decoder/test/test_decoder_gas.py | 8 ++++---- src/soc/decoder/test/test_power_decoder.py | 4 ++-- src/soc/experiment/alu_hier.py | 4 ++-- src/soc/experiment/compalu.py | 6 +++--- src/soc/experiment/compldst_multi.py | 4 ++-- src/soc/experiment/l0_cache.py | 6 +++--- src/soc/experiment/pimem.py | 2 +- src/soc/experiment/score6600.py | 8 ++++---- src/soc/experiment/score6600_multi.py | 10 +++++----- src/soc/experiment/sim.py | 2 +- src/soc/experiment/test/test_compalu_multi.py | 2 +- src/soc/fu/alu/alu_input_record.py | 2 +- src/soc/fu/alu/formal/proof_input_stage.py | 2 +- src/soc/fu/alu/formal/proof_main_stage.py | 2 +- src/soc/fu/alu/formal/proof_output_stage.py | 2 +- src/soc/fu/alu/main_stage.py | 6 +++--- src/soc/fu/alu/output_stage.py | 2 +- src/soc/fu/alu/test/svp64_cases.py | 4 ++-- src/soc/fu/alu/test/test_pipe_caller.py | 14 +++++++------- src/soc/fu/branch/br_input_record.py | 2 +- src/soc/fu/branch/formal/proof_input_stage.py | 2 +- src/soc/fu/branch/formal/proof_main_stage.py | 2 +- src/soc/fu/branch/main_stage.py | 6 +++--- src/soc/fu/branch/test/test_pipe_caller.py | 14 +++++++------- src/soc/fu/common_input_stage.py | 4 ++-- src/soc/fu/common_output_stage.py | 2 +- src/soc/fu/compunits/compunits.py | 2 +- src/soc/fu/compunits/formal/test_compunit.py | 2 +- src/soc/fu/compunits/test/test_alu_compunit.py | 2 +- .../fu/compunits/test/test_branch_compunit.py | 2 +- src/soc/fu/compunits/test/test_compunit.py | 8 ++++---- src/soc/fu/compunits/test/test_cr_compunit.py | 2 +- src/soc/fu/compunits/test/test_div_compunit.py | 2 +- src/soc/fu/compunits/test/test_ldst_compunit.py | 2 +- .../fu/compunits/test/test_logical_compunit.py | 2 +- .../fu/compunits/test/test_shiftrot_compunit.py | 2 +- src/soc/fu/compunits/test/test_spr_compunit.py | 2 +- src/soc/fu/compunits/test/test_trap_compunit.py | 2 +- src/soc/fu/cr/cr_input_record.py | 2 +- src/soc/fu/cr/formal/proof_main_stage.py | 2 +- src/soc/fu/cr/main_stage.py | 6 +++--- src/soc/fu/cr/test/test_pipe_caller.py | 14 +++++++------- src/soc/fu/div/core_stages.py | 6 +++--- src/soc/fu/div/formal/proof_main_stage.py | 2 +- src/soc/fu/div/output_stage.py | 6 +++--- src/soc/fu/div/setup_stage.py | 6 +++--- src/soc/fu/div/test/helper.py | 8 ++++---- src/soc/fu/div/test/test_pipe_caller.py | 2 +- src/soc/fu/div/test/test_pipe_caller_long.py | 2 +- src/soc/fu/ldst/ldst_input_record.py | 2 +- src/soc/fu/ldst/test/test_pipe_caller.py | 14 +++++++------- src/soc/fu/logical/formal/proof_input_stage.py | 2 +- src/soc/fu/logical/formal/proof_main_stage.py | 2 +- src/soc/fu/logical/logical_input_record.py | 2 +- src/soc/fu/logical/main_stage.py | 6 +++--- src/soc/fu/logical/output_stage.py | 2 +- src/soc/fu/logical/test/test_pipe_caller.py | 14 +++++++------- src/soc/fu/mmu/fsm.py | 8 ++++---- src/soc/fu/mmu/mmu_input_record.py | 2 +- src/soc/fu/mmu/test/test_issuer_mmu_data_path.py | 2 +- src/soc/fu/mmu/test/test_issuer_mmu_rom.py | 2 +- src/soc/fu/mmu/test/test_non_production_core.py | 14 +++++++------- src/soc/fu/mmu/test/test_pipe_caller.py | 14 +++++++------- src/soc/fu/mul/formal/proof_main_stage.py | 6 +++--- src/soc/fu/mul/mul_input_record.py | 2 +- src/soc/fu/mul/post_stage.py | 2 +- src/soc/fu/mul/test/helper.py | 14 +++++++------- src/soc/fu/mul/test/test_pipe_caller.py | 2 +- src/soc/fu/mul/test/test_pipe_caller_long.py | 2 +- src/soc/fu/pipe_data.py | 2 +- src/soc/fu/shift_rot/formal/proof_main_stage.py | 2 +- src/soc/fu/shift_rot/main_stage.py | 6 +++--- src/soc/fu/shift_rot/sr_input_record.py | 2 +- src/soc/fu/shift_rot/test/test_maskgen.py | 2 +- src/soc/fu/shift_rot/test/test_pipe_caller.py | 14 +++++++------- src/soc/fu/spr/formal/proof_main_stage.py | 8 ++++---- src/soc/fu/spr/main_stage.py | 8 ++++---- src/soc/fu/spr/spr_input_record.py | 2 +- src/soc/fu/spr/test/test_pipe_caller.py | 14 +++++++------- src/soc/fu/test/common.py | 2 +- src/soc/fu/trap/formal/proof_main_stage.py | 2 +- src/soc/fu/trap/main_stage.py | 6 +++--- src/soc/fu/trap/test/test_pipe_caller.py | 14 +++++++------- src/soc/fu/trap/trap_input_record.py | 2 +- src/soc/regfile/regfiles.py | 2 +- src/soc/regfile/util.py | 2 +- src/soc/scoreboard/instruction_q.py | 2 +- src/soc/simple/core.py | 16 ++++++++-------- src/soc/simple/issuer.py | 12 ++++++------ src/soc/simple/test/test_core.py | 14 +++++++------- src/soc/simple/test/test_issuer.py | 4 ++-- src/soc/simple/test/test_microwatt.py | 4 ++-- src/soc/simple/test/test_runner.py | 10 +++++----- src/soc/sv/trans/svp64.py | 8 ++++---- 106 files changed, 273 insertions(+), 273 deletions(-) diff --git a/src/soc/debug/firmware_upload.py b/src/soc/debug/firmware_upload.py index 053b3860..05fe4879 100644 --- a/src/soc/debug/firmware_upload.py +++ b/src/soc/debug/firmware_upload.py @@ -21,7 +21,7 @@ from nmutil.util import wrap from soc.debug.jtagutils import (jtag_read_write_reg, jtag_srv, jtag_set_reset, jtag_set_ir, jtag_set_get_dr) -from soc.simulator.program import Program +from openpower.simulator.program import Program def test_pinset(): return { diff --git a/src/soc/decoder/formal/proof_decoder.py b/src/soc/decoder/formal/proof_decoder.py index 5abd9182..ce19a426 100644 --- a/src/soc/decoder/formal/proof_decoder.py +++ b/src/soc/decoder/formal/proof_decoder.py @@ -2,12 +2,12 @@ from nmigen import Module, Signal, Elaboratable, Cat from nmigen.asserts import Assert, AnyConst, Assume from nmutil.formaltest import FHDLTestCase -from soc.decoder.power_decoder import create_pdecode, PowerOp -from soc.decoder.power_enums import (In1Sel, In2Sel, In3Sel, +from openpower.decoder.power_decoder import create_pdecode, PowerOp +from openpower.decoder.power_enums import (In1Sel, In2Sel, In3Sel, OutSel, RC, Form, Function, LdstLen, CryIn, MicrOp, SPR, get_csv) -from soc.decoder.power_decoder2 import (PowerDecode2, +from openpower.decoder.power_decoder2 import (PowerDecode2, Decode2ToExecute1Type) import unittest import pdb diff --git a/src/soc/decoder/formal/proof_decoder2.py b/src/soc/decoder/formal/proof_decoder2.py index b7ac61f7..d20c28f1 100644 --- a/src/soc/decoder/formal/proof_decoder2.py +++ b/src/soc/decoder/formal/proof_decoder2.py @@ -2,11 +2,11 @@ from nmigen import Module, Signal, Elaboratable, Cat, Repl from nmigen.asserts import Assert, AnyConst from nmutil.formaltest import FHDLTestCase -from soc.decoder.power_decoder import create_pdecode, PowerOp -from soc.decoder.power_enums import (In1Sel, In2Sel, In3Sel, +from openpower.decoder.power_decoder import create_pdecode, PowerOp +from openpower.decoder.power_enums import (In1Sel, In2Sel, In3Sel, OutSel, RC, Form, MicrOp, SPR) -from soc.decoder.power_decoder2 import (PowerDecode2, +from openpower.decoder.power_decoder2 import (PowerDecode2, Decode2ToExecute1Type) import unittest diff --git a/src/soc/decoder/helpers.py b/src/soc/decoder/helpers.py index 6f63cc3d..b54bcfd8 100644 --- a/src/soc/decoder/helpers.py +++ b/src/soc/decoder/helpers.py @@ -1,10 +1,10 @@ import unittest -from soc.decoder.selectable_int import SelectableInt, onebit +from openpower.decoder.selectable_int import SelectableInt, onebit from nmutil.divmod import trunc_divs, trunc_rems from operator import floordiv, mod -from soc.decoder.selectable_int import selectltu as ltu -from soc.decoder.selectable_int import selectgtu as gtu -from soc.decoder.selectable_int import check_extsign +from openpower.decoder.selectable_int import selectltu as ltu +from openpower.decoder.selectable_int import selectgtu as gtu +from openpower.decoder.selectable_int import check_extsign trunc_div = floordiv trunc_rem = mod diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index 315db251..f19769f3 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -16,24 +16,24 @@ related bugs: from nmigen.back.pysim import Settle from functools import wraps from copy import copy -from soc.decoder.orderedset import OrderedSet -from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt, +from openpower.decoder.orderedset import OrderedSet +from openpower.decoder.selectable_int import (FieldSelectableInt, SelectableInt, selectconcat) -from soc.decoder.power_enums import (spr_dict, spr_byname, XER_bits, +from openpower.decoder.power_enums import (spr_dict, spr_byname, XER_bits, insns, MicrOp, In1Sel, In2Sel, In3Sel, OutSel, CROutSel, SVP64RMMode, SVP64PredMode, SVP64PredInt, SVP64PredCR) -from soc.decoder.power_enums import SVPtype +from openpower.decoder.power_enums import SVPtype -from soc.decoder.helpers import exts, gtu, ltu, undefined +from openpower.decoder.helpers import exts, gtu, ltu, undefined from soc.consts import PIb, MSRb # big-endian (PowerISA versions) from soc.consts import SVP64CROffs -from soc.decoder.power_svp64 import SVP64RM, decode_extra +from openpower.decoder.power_svp64 import SVP64RM, decode_extra -from soc.decoder.isa.radixmmu import RADIX -from soc.decoder.isa.mem import Mem, swap_order +from openpower.decoder.isa.radixmmu import RADIX +from openpower.decoder.isa.mem import Mem, swap_order from collections import namedtuple import math diff --git a/src/soc/decoder/power_pseudo.py b/src/soc/decoder/power_pseudo.py index 3e02cb78..eb87b626 100644 --- a/src/soc/decoder/power_pseudo.py +++ b/src/soc/decoder/power_pseudo.py @@ -15,13 +15,13 @@ from ply import lex, yacc import astor import ast -from soc.decoder.power_decoder import create_pdecode +from openpower.decoder.power_decoder import create_pdecode from nmigen.back.pysim import Simulator, Delay from nmigen import Module, Signal -from soc.decoder.pseudo.parser import GardenSnakeCompiler -from soc.decoder.selectable_int import SelectableInt, selectconcat -from soc.decoder.isa.caller import GPR, Mem +from openpower.decoder.pseudo.parser import GardenSnakeCompiler +from openpower.decoder.selectable_int import SelectableInt, selectconcat +from openpower.decoder.isa.caller import GPR, Mem ####### Test code ####### @@ -256,7 +256,7 @@ def test(): print("args", args) print("-->", " ".join(map(str, args))) - from soc.decoder.helpers import (EXTS64, EXTZ64, ROTL64, ROTL32, MASK, + from openpower.decoder.helpers import (EXTS64, EXTZ64, ROTL64, ROTL32, MASK, trunc_div, trunc_rem) d = {} diff --git a/src/soc/decoder/power_regspec_map.py b/src/soc/decoder/power_regspec_map.py index 05ff4814..0f5bce32 100644 --- a/src/soc/decoder/power_regspec_map.py +++ b/src/soc/decoder/power_regspec_map.py @@ -36,7 +36,7 @@ see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs """ from nmigen import Const from soc.regfile.regfiles import XERRegs, FastRegs, StateRegs -from soc.decoder.power_enums import CryIn +from openpower.decoder.power_enums import CryIn def regspec_decode_read(e, regfile, name): diff --git a/src/soc/decoder/power_svp64.py b/src/soc/decoder/power_svp64.py index 167053c9..3e3332ea 100644 --- a/src/soc/decoder/power_svp64.py +++ b/src/soc/decoder/power_svp64.py @@ -2,7 +2,7 @@ # Copyright (C) 2021 Luke Kenneth Casson Leighton # Funded by NLnet http://nlnet.nl -from soc.decoder.power_enums import get_csv, find_wiki_dir +from openpower.decoder.power_enums import get_csv, find_wiki_dir import os # identifies register by type diff --git a/src/soc/decoder/power_svp64_extra.py b/src/soc/decoder/power_svp64_extra.py index 02c0bfd5..1ac3c52b 100644 --- a/src/soc/decoder/power_svp64_extra.py +++ b/src/soc/decoder/power_svp64_extra.py @@ -6,7 +6,7 @@ from nmigen.cli import rtlil from nmutil.util import sel -from soc.decoder.power_enums import (SVEXTRA, SVEtype) +from openpower.decoder.power_enums import (SVEXTRA, SVEtype) from soc.consts import (SPEC, EXTRA2, EXTRA3, SVP64P, field, SPEC_SIZE, SPECb, SPEC_AUG_SIZE, SVP64CROffs) diff --git a/src/soc/decoder/power_svp64_rm.py b/src/soc/decoder/power_svp64_rm.py index ac29159a..16b0116a 100644 --- a/src/soc/decoder/power_svp64_rm.py +++ b/src/soc/decoder/power_svp64_rm.py @@ -17,7 +17,7 @@ https://libre-soc.org/openpower/sv/svp64/ """ from nmigen import Elaboratable, Module, Signal, Const -from soc.decoder.power_enums import (SVP64RMMode, Function, SVPtype, +from openpower.decoder.power_enums import (SVP64RMMode, Function, SVPtype, SVP64PredMode, SVP64sat) from soc.consts import EXTRA3, SVP64MODE from soc.sv.svp64 import SVP64Rec diff --git a/src/soc/decoder/pseudo/lexer.py b/src/soc/decoder/pseudo/lexer.py index 43aab336..b420798b 100644 --- a/src/soc/decoder/pseudo/lexer.py +++ b/src/soc/decoder/pseudo/lexer.py @@ -10,7 +10,7 @@ # Modifications for inclusion in PLY distribution from copy import copy from ply import lex -from soc.decoder.selectable_int import SelectableInt +from openpower.decoder.selectable_int import SelectableInt # I implemented INDENT / DEDENT generation as a post-processing filter diff --git a/src/soc/decoder/pseudo/parser.py b/src/soc/decoder/pseudo/parser.py index 54b2635c..0e671960 100644 --- a/src/soc/decoder/pseudo/parser.py +++ b/src/soc/decoder/pseudo/parser.py @@ -13,9 +13,9 @@ from ply import lex, yacc import astor from copy import deepcopy -from soc.decoder.power_decoder import create_pdecode -from soc.decoder.pseudo.lexer import IndentLexer -from soc.decoder.orderedset import OrderedSet +from openpower.decoder.power_decoder import create_pdecode +from openpower.decoder.pseudo.lexer import IndentLexer +from openpower.decoder.orderedset import OrderedSet # I use the Python AST #from compiler import ast diff --git a/src/soc/decoder/test/test_decoder_gas.py b/src/soc/decoder/test/test_decoder_gas.py index f65abfac..fdbf8a31 100644 --- a/src/soc/decoder/test/test_decoder_gas.py +++ b/src/soc/decoder/test/test_decoder_gas.py @@ -6,14 +6,14 @@ from nmutil.sim_tmp_alternative import Simulator, Delay from nmutil.formaltest import FHDLTestCase import unittest -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_enums import (Function, MicrOp, +from openpower.decoder.power_decoder import (create_pdecode) +from openpower.decoder.power_enums import (Function, MicrOp, In1Sel, In2Sel, In3Sel, OutSel, RC, LdstLen, CryIn, single_bit_flags, Form, SPR, get_signal_name, get_csv) -from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.simulator.gas import get_assembled_instruction +from openpower.decoder.power_decoder2 import (PowerDecode2) +from openpower.simulator.gas import get_assembled_instruction import random diff --git a/src/soc/decoder/test/test_power_decoder.py b/src/soc/decoder/test/test_power_decoder.py index 0a18c77b..8ee9a554 100644 --- a/src/soc/decoder/test/test_power_decoder.py +++ b/src/soc/decoder/test/test_power_decoder.py @@ -8,8 +8,8 @@ from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil import os import unittest -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_enums import (Function, MicrOp, +from openpower.decoder.power_decoder import (create_pdecode) +from openpower.decoder.power_enums import (Function, MicrOp, In1Sel, In2Sel, In3Sel, CRInSel, CROutSel, OutSel, RC, LdstLen, CryIn, diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py index 7aecaf69..dbe8465f 100644 --- a/src/soc/experiment/alu_hier.py +++ b/src/soc/experiment/alu_hier.py @@ -22,8 +22,8 @@ from nmutil.gtkw import write_gtkw from nmutil.sim_tmp_alternative import (Simulator, nmigen_sim_top_module, is_engine_pysim) -from soc.decoder.decode2execute1 import Data -from soc.decoder.power_enums import MicrOp, Function, CryIn +from openpower.decoder.decode2execute1 import Data +from openpower.decoder.power_enums import MicrOp, Function, CryIn from soc.fu.alu.alu_input_record import CompALUOpSubset from soc.fu.cr.cr_input_record import CompCROpSubset diff --git a/src/soc/experiment/compalu.py b/src/soc/experiment/compalu.py index 89d2da1a..05539cd4 100644 --- a/src/soc/experiment/compalu.py +++ b/src/soc/experiment/compalu.py @@ -3,8 +3,8 @@ from nmigen.cli import verilog, rtlil from nmigen import Module, Signal, Mux, Elaboratable from nmutil.latch import SRLatch, latchregister -from soc.decoder.power_decoder2 import Data -from soc.decoder.power_enums import MicrOp +from openpower.decoder.power_decoder2 import Data +from openpower.decoder.power_enums import MicrOp from soc.experiment.alu_hier import CompALUOpSubset @@ -224,7 +224,7 @@ def scoreboard_sim(dut): def test_scoreboard(): from alu_hier import ALU - from soc.decoder.power_decoder2 import Decode2ToExecute1Type + from openpower.decoder.power_decoder2 import Decode2ToExecute1Type alu = ALU(16) dut = ComputationUnitNoDelay(16, alu) diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py index 8e9f4ec3..807d15bf 100644 --- a/src/soc/experiment/compldst_multi.py +++ b/src/soc/experiment/compldst_multi.py @@ -92,9 +92,9 @@ from soc.experiment.l0_cache import PortInterface from soc.experiment.pimem import LDSTException from soc.fu.regspec import RegSpecAPI -from soc.decoder.power_enums import MicrOp, Function, LDSTMode +from openpower.decoder.power_enums import MicrOp, Function, LDSTMode from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset -from soc.decoder.power_decoder2 import Data +from openpower.decoder.power_decoder2 import Data class LDSTCompUnitRecord(CompUnitRecord): diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py index e2c31096..e4f02513 100644 --- a/src/soc/experiment/l0_cache.py +++ b/src/soc/experiment/l0_cache.py @@ -23,12 +23,12 @@ from nmigen.utils import log2_int from nmigen.hdl.rec import Record, Layout from nmutil.latch import SRLatch, latchregister -from soc.decoder.power_decoder2 import Data -from soc.decoder.power_enums import MicrOp +from openpower.decoder.power_decoder2 import Data +from openpower.decoder.power_enums import MicrOp from soc.regfile.regfile import ortreereduce from nmutil.util import treereduce -from soc.decoder.power_decoder2 import Data +from openpower.decoder.power_decoder2 import Data #from nmutil.picker import PriorityPicker from nmigen.lib.coding import PriorityEncoder from soc.scoreboard.addr_split import LDSTSplitter diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py index f8a05992..1a66b914 100644 --- a/src/soc/experiment/pimem.py +++ b/src/soc/experiment/pimem.py @@ -23,7 +23,7 @@ from nmigen.utils import log2_int from nmutil.latch import SRLatch, latchregister from nmutil.util import rising_edge -from soc.decoder.power_decoder2 import Data +from openpower.decoder.power_decoder2 import Data from soc.scoreboard.addr_match import LenExpand from soc.experiment.mem_types import LDSTException diff --git a/src/soc/experiment/score6600.py b/src/soc/experiment/score6600.py index 33388084..f5366961 100644 --- a/src/soc/experiment/score6600.py +++ b/src/soc/experiment/score6600.py @@ -20,10 +20,10 @@ from soc.experiment.testmem import TestMemory from soc.experiment.alu_hier import ALU, BranchALU, CompALUOpSubset -from soc.decoder.power_enums import MicrOp, Function -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.simulator.program import Program +from openpower.decoder.power_enums import MicrOp, Function +from openpower.decoder.power_decoder import (create_pdecode) +from openpower.decoder.power_decoder2 import (PowerDecode2) +from openpower.simulator.program import Program from nmutil.latch import SRLatch diff --git a/src/soc/experiment/score6600_multi.py b/src/soc/experiment/score6600_multi.py index 22d8e2d1..85b8b45c 100644 --- a/src/soc/experiment/score6600_multi.py +++ b/src/soc/experiment/score6600_multi.py @@ -23,12 +23,12 @@ from soc.experiment.l0_cache import TstL0CacheBuffer from soc.experiment.alu_hier import ALU, BranchALU from soc.fu.alu.alu_input_record import CompALUOpSubset -from soc.decoder.power_enums import MicrOp, Function -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.decoder.power_decoder2 import Decode2ToExecute1Type +from openpower.decoder.power_enums import MicrOp, Function +from openpower.decoder.power_decoder import (create_pdecode) +from openpower.decoder.power_decoder2 import (PowerDecode2) +from openpower.decoder.power_decoder2 import Decode2ToExecute1Type -from soc.simulator.program import Program +from openpower.simulator.program import Program from nmutil.latch import SRLatch diff --git a/src/soc/experiment/sim.py b/src/soc/experiment/sim.py index aebb51de..0547bda6 100644 --- a/src/soc/experiment/sim.py +++ b/src/soc/experiment/sim.py @@ -1,4 +1,4 @@ -from soc.decoder.power_enums import MicrOp +from openpower.decoder.power_enums import MicrOp from random import randint, seed from copy import deepcopy diff --git a/src/soc/experiment/test/test_compalu_multi.py b/src/soc/experiment/test/test_compalu_multi.py index 95482721..2f858b6c 100644 --- a/src/soc/experiment/test/test_compalu_multi.py +++ b/src/soc/experiment/test/test_compalu_multi.py @@ -15,7 +15,7 @@ from soc.fu.alu.alu_input_record import CompALUOpSubset from soc.fu.cr.cr_input_record import CompCROpSubset from soc.experiment.alu_hier import ALU, DummyALU from soc.experiment.compalu_multi import MultiCompUnit -from soc.decoder.power_enums import MicrOp +from openpower.decoder.power_enums import MicrOp from nmutil.gtkw import write_gtkw from nmigen import Module, Signal from nmigen.cli import rtlil diff --git a/src/soc/fu/alu/alu_input_record.py b/src/soc/fu/alu/alu_input_record.py index fdafee52..4126fc6c 100644 --- a/src/soc/fu/alu/alu_input_record.py +++ b/src/soc/fu/alu/alu_input_record.py @@ -1,5 +1,5 @@ from soc.fu.base_input_record import CompOpSubsetBase -from soc.decoder.power_enums import MicrOp, Function, CryIn +from openpower.decoder.power_enums import MicrOp, Function, CryIn from nmigen.hdl.rec import Layout diff --git a/src/soc/fu/alu/formal/proof_input_stage.py b/src/soc/fu/alu/formal/proof_input_stage.py index afa39b13..107be930 100644 --- a/src/soc/fu/alu/formal/proof_input_stage.py +++ b/src/soc/fu/alu/formal/proof_input_stage.py @@ -9,7 +9,7 @@ from nmigen.cli import rtlil from soc.fu.alu.input_stage import ALUInputStage from soc.fu.alu.pipe_data import ALUPipeSpec from soc.fu.alu.alu_input_record import CompALUOpSubset -from soc.decoder.power_enums import MicrOp +from openpower.decoder.power_enums import MicrOp import unittest diff --git a/src/soc/fu/alu/formal/proof_main_stage.py b/src/soc/fu/alu/formal/proof_main_stage.py index a5e8e12f..529381ea 100644 --- a/src/soc/fu/alu/formal/proof_main_stage.py +++ b/src/soc/fu/alu/formal/proof_main_stage.py @@ -16,7 +16,7 @@ from nmigen.cli import rtlil from soc.fu.alu.main_stage import ALUMainStage from soc.fu.alu.pipe_data import ALUPipeSpec from soc.fu.alu.alu_input_record import CompALUOpSubset -from soc.decoder.power_enums import MicrOp +from openpower.decoder.power_enums import MicrOp import unittest diff --git a/src/soc/fu/alu/formal/proof_output_stage.py b/src/soc/fu/alu/formal/proof_output_stage.py index 7dd3f383..5e32fbfd 100644 --- a/src/soc/fu/alu/formal/proof_output_stage.py +++ b/src/soc/fu/alu/formal/proof_output_stage.py @@ -15,7 +15,7 @@ from nmigen.cli import rtlil from soc.fu.alu.output_stage import ALUOutputStage from soc.fu.alu.pipe_data import ALUPipeSpec from soc.fu.alu.alu_input_record import CompALUOpSubset -from soc.decoder.power_enums import MicrOp +from openpower.decoder.power_enums import MicrOp import unittest diff --git a/src/soc/fu/alu/main_stage.py b/src/soc/fu/alu/main_stage.py index 9e282c8c..4d5fe231 100644 --- a/src/soc/fu/alu/main_stage.py +++ b/src/soc/fu/alu/main_stage.py @@ -14,10 +14,10 @@ from nmutil.pipemodbase import PipeModBase from nmutil.extend import exts, extz from soc.fu.alu.pipe_data import ALUInputData, ALUOutputData from ieee754.part.partsig import PartitionedSignal -from soc.decoder.power_enums import MicrOp +from openpower.decoder.power_enums import MicrOp -from soc.decoder.power_fields import DecodeFields -from soc.decoder.power_fieldsn import SignalBitRange +from openpower.decoder.power_fields import DecodeFields +from openpower.decoder.power_fieldsn import SignalBitRange # microwatt calc_ov function. diff --git a/src/soc/fu/alu/output_stage.py b/src/soc/fu/alu/output_stage.py index 2cf8c325..49444e97 100644 --- a/src/soc/fu/alu/output_stage.py +++ b/src/soc/fu/alu/output_stage.py @@ -5,7 +5,7 @@ from nmigen import (Module, Signal, Cat, Repl) from soc.fu.alu.pipe_data import ALUInputData, ALUOutputData from soc.fu.common_output_stage import CommonOutputStage from ieee754.part.partsig import PartitionedSignal -from soc.decoder.power_enums import MicrOp +from openpower.decoder.power_enums import MicrOp class ALUOutputStage(CommonOutputStage): diff --git a/src/soc/fu/alu/test/svp64_cases.py b/src/soc/fu/alu/test/svp64_cases.py index 72c982fd..15f4211c 100644 --- a/src/soc/fu/alu/test/svp64_cases.py +++ b/src/soc/fu/alu/test/svp64_cases.py @@ -1,7 +1,7 @@ from soc.fu.test.common import (TestAccumulatorBase, skip_case) from soc.config.endian import bigendian -from soc.simulator.program import Program -from soc.decoder.isa.caller import SVP64State +from openpower.simulator.program import Program +from openpower.decoder.isa.caller import SVP64State from soc.sv.trans.svp64 import SVP64Asm diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py index e8edc2f9..e117f9c1 100644 --- a/src/soc/fu/alu/test/test_pipe_caller.py +++ b/src/soc/fu/alu/test/test_pipe_caller.py @@ -3,13 +3,13 @@ from soc.fu.alu.pipe_data import ALUPipeSpec from soc.fu.alu.pipeline import ALUBasePipe from soc.fu.test.common import (TestCase, TestAccumulatorBase, ALUHelpers) from soc.config.endian import bigendian -from soc.decoder.isa.all import ISA -from soc.simulator.program import Program -from soc.decoder.selectable_int import SelectableInt -from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn) -from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.isa.caller import special_sprs +from openpower.decoder.isa.all import ISA +from openpower.simulator.program import Program +from openpower.decoder.selectable_int import SelectableInt +from openpower.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn) +from openpower.decoder.power_decoder2 import (PowerDecode2) +from openpower.decoder.power_decoder import (create_pdecode) +from openpower.decoder.isa.caller import special_sprs import unittest from nmigen.cli import rtlil from nmutil.formaltest import FHDLTestCase diff --git a/src/soc/fu/branch/br_input_record.py b/src/soc/fu/branch/br_input_record.py index 41665488..a27358b8 100644 --- a/src/soc/fu/branch/br_input_record.py +++ b/src/soc/fu/branch/br_input_record.py @@ -1,7 +1,7 @@ from soc.fu.base_input_record import CompOpSubsetBase from nmigen.hdl.rec import Layout -from soc.decoder.power_enums import MicrOp, Function +from openpower.decoder.power_enums import MicrOp, Function class CompBROpSubset(CompOpSubsetBase): diff --git a/src/soc/fu/branch/formal/proof_input_stage.py b/src/soc/fu/branch/formal/proof_input_stage.py index 89346e21..780fcbea 100644 --- a/src/soc/fu/branch/formal/proof_input_stage.py +++ b/src/soc/fu/branch/formal/proof_input_stage.py @@ -9,7 +9,7 @@ from nmigen.cli import rtlil from soc.fu.alu.input_stage import ALUInputStage from soc.fu.alu.pipe_data import ALUPipeSpec from soc.fu.branch.br_input_record import CompBROpSubset -from soc.decoder.power_enums import MicrOp +from openpower.decoder.power_enums import MicrOp import unittest diff --git a/src/soc/fu/branch/formal/proof_main_stage.py b/src/soc/fu/branch/formal/proof_main_stage.py index fcb214a3..94cf0024 100644 --- a/src/soc/fu/branch/formal/proof_main_stage.py +++ b/src/soc/fu/branch/formal/proof_main_stage.py @@ -16,7 +16,7 @@ from nmigen.cli import rtlil from soc.fu.branch.main_stage import BranchMainStage from soc.fu.branch.pipe_data import BranchPipeSpec from soc.fu.branch.br_input_record import CompBROpSubset -from soc.decoder.power_enums import MicrOp +from openpower.decoder.power_enums import MicrOp import unittest diff --git a/src/soc/fu/branch/main_stage.py b/src/soc/fu/branch/main_stage.py index bf18db72..13bd7902 100644 --- a/src/soc/fu/branch/main_stage.py +++ b/src/soc/fu/branch/main_stage.py @@ -32,10 +32,10 @@ from nmigen import (Module, Signal, Cat, Mux, Const, Array) from nmutil.pipemodbase import PipeModBase from nmutil.extend import exts from soc.fu.branch.pipe_data import BranchInputData, BranchOutputData -from soc.decoder.power_enums import MicrOp +from openpower.decoder.power_enums import MicrOp -from soc.decoder.power_fields import DecodeFields -from soc.decoder.power_fieldsn import SignalBitRange +from openpower.decoder.power_fields import DecodeFields +from openpower.decoder.power_fieldsn import SignalBitRange def br_ext(bd): diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py index cf13bcf2..53d27cc0 100644 --- a/src/soc/fu/branch/test/test_pipe_caller.py +++ b/src/soc/fu/branch/test/test_pipe_caller.py @@ -6,13 +6,13 @@ from nmutil.sim_tmp_alternative import Simulator, Settle from nmigen.cli import rtlil import unittest -from soc.decoder.isa.caller import ISACaller, special_sprs -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.decoder.power_enums import (XER_bits, Function, MicrOp) -from soc.decoder.selectable_int import SelectableInt -from soc.simulator.program import Program -from soc.decoder.isa.all import ISA +from openpower.decoder.isa.caller import ISACaller, special_sprs +from openpower.decoder.power_decoder import (create_pdecode) +from openpower.decoder.power_decoder2 import (PowerDecode2) +from openpower.decoder.power_enums import (XER_bits, Function, MicrOp) +from openpower.decoder.selectable_int import SelectableInt +from openpower.simulator.program import Program +from openpower.decoder.isa.all import ISA from soc.regfile.regfiles import FastRegs from soc.config.endian import bigendian diff --git a/src/soc/fu/common_input_stage.py b/src/soc/fu/common_input_stage.py index e36b14db..09a02006 100644 --- a/src/soc/fu/common_input_stage.py +++ b/src/soc/fu/common_input_stage.py @@ -3,8 +3,8 @@ # generation for subtraction, should happen here from nmigen import (Module, Signal) from nmutil.pipemodbase import PipeModBase -from soc.decoder.power_enums import MicrOp -from soc.decoder.power_enums import CryIn +from openpower.decoder.power_enums import MicrOp +from openpower.decoder.power_enums import CryIn class CommonInputStage(PipeModBase): diff --git a/src/soc/fu/common_output_stage.py b/src/soc/fu/common_output_stage.py index 5a8b2f78..e5cf3a30 100644 --- a/src/soc/fu/common_output_stage.py +++ b/src/soc/fu/common_output_stage.py @@ -3,7 +3,7 @@ from nmigen import (Module, Signal, Cat, Const) from nmutil.pipemodbase import PipeModBase from ieee754.part.partsig import PartitionedSignal -from soc.decoder.power_enums import MicrOp +from openpower.decoder.power_enums import MicrOp class CommonOutputStage(PipeModBase): diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py index a33801b0..cd3bf716 100644 --- a/src/soc/fu/compunits/compunits.py +++ b/src/soc/fu/compunits/compunits.py @@ -46,7 +46,7 @@ see: from nmigen import Elaboratable, Module from nmigen.cli import rtlil from soc.experiment.compalu_multi import MultiCompUnit -from soc.decoder.power_enums import Function +from openpower.decoder.power_enums import Function from soc.config.test.test_loadstore import TestMemPspec # pipeline / spec imports diff --git a/src/soc/fu/compunits/formal/test_compunit.py b/src/soc/fu/compunits/formal/test_compunit.py index 153879ba..350a611c 100644 --- a/src/soc/fu/compunits/formal/test_compunit.py +++ b/src/soc/fu/compunits/formal/test_compunit.py @@ -6,7 +6,7 @@ from soc.fu.compunits.compunits import FunctionUnitBaseSingle from soc.experiment.alu_hier import DummyALU from soc.experiment.compalu_multi import MultiCompUnit from soc.fu.alu.alu_input_record import CompALUOpSubset -from soc.decoder.power_enums import MicrOp +from openpower.decoder.power_enums import MicrOp import unittest class MaskGenTestCase(FHDLTestCase): diff --git a/src/soc/fu/compunits/test/test_alu_compunit.py b/src/soc/fu/compunits/test/test_alu_compunit.py index bed6202d..73f84ee9 100644 --- a/src/soc/fu/compunits/test/test_alu_compunit.py +++ b/src/soc/fu/compunits/test/test_alu_compunit.py @@ -1,5 +1,5 @@ import unittest -from soc.decoder.power_enums import (XER_bits, Function) +from openpower.decoder.power_enums import (XER_bits, Function) from soc.fu.alu.test.test_pipe_caller import get_cu_inputs from soc.fu.alu.test.test_pipe_caller import ALUTestCase # creates the tests diff --git a/src/soc/fu/compunits/test/test_branch_compunit.py b/src/soc/fu/compunits/test/test_branch_compunit.py index c570debe..7c85050e 100644 --- a/src/soc/fu/compunits/test/test_branch_compunit.py +++ b/src/soc/fu/compunits/test/test_branch_compunit.py @@ -1,5 +1,5 @@ import unittest -from soc.decoder.power_enums import (XER_bits, Function, spr_dict, SPR) +from openpower.decoder.power_enums import (XER_bits, Function, spr_dict, SPR) from soc.fu.branch.test.test_pipe_caller import BranchTestCase, get_cu_inputs diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py index b1511f88..2031b20e 100644 --- a/src/soc/fu/compunits/test/test_compunit.py +++ b/src/soc/fu/compunits/test/test_compunit.py @@ -7,10 +7,10 @@ from nmutil.sim_tmp_alternative import Simulator, Settle from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil import unittest -from soc.decoder.power_decoder import create_pdecode -from soc.decoder.power_decoder2 import PowerDecode2, get_rdflags -from soc.decoder.power_enums import Function -from soc.decoder.isa.all import ISA +from openpower.decoder.power_decoder import create_pdecode +from openpower.decoder.power_decoder2 import PowerDecode2, get_rdflags +from openpower.decoder.power_enums import Function +from openpower.decoder.isa.all import ISA from soc.experiment.compalu_multi import find_ok # hack from soc.config.test.test_loadstore import TestMemPspec diff --git a/src/soc/fu/compunits/test/test_cr_compunit.py b/src/soc/fu/compunits/test/test_cr_compunit.py index 4e59fe3e..6dc3dfdc 100644 --- a/src/soc/fu/compunits/test/test_cr_compunit.py +++ b/src/soc/fu/compunits/test/test_cr_compunit.py @@ -1,5 +1,5 @@ import unittest -from soc.decoder.power_enums import (XER_bits, Function) +from openpower.decoder.power_enums import (XER_bits, Function) # XXX bad practice: use of global variables from soc.fu.cr.test.test_pipe_caller import get_cu_inputs diff --git a/src/soc/fu/compunits/test/test_div_compunit.py b/src/soc/fu/compunits/test/test_div_compunit.py index 35fc1ab1..06375b15 100644 --- a/src/soc/fu/compunits/test/test_div_compunit.py +++ b/src/soc/fu/compunits/test/test_div_compunit.py @@ -1,5 +1,5 @@ import unittest -from soc.decoder.power_enums import (XER_bits, Function) +from openpower.decoder.power_enums import (XER_bits, Function) from soc.fu.div.test.test_pipe_caller import get_cu_inputs from soc.fu.div.test.test_pipe_caller import DivTestCases # creates the tests diff --git a/src/soc/fu/compunits/test/test_ldst_compunit.py b/src/soc/fu/compunits/test/test_ldst_compunit.py index a5fff3c2..b394a4fb 100644 --- a/src/soc/fu/compunits/test/test_ldst_compunit.py +++ b/src/soc/fu/compunits/test/test_ldst_compunit.py @@ -1,5 +1,5 @@ import unittest -from soc.decoder.power_enums import (XER_bits, Function) +from openpower.decoder.power_enums import (XER_bits, Function) from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase, get_cu_inputs diff --git a/src/soc/fu/compunits/test/test_logical_compunit.py b/src/soc/fu/compunits/test/test_logical_compunit.py index 6dfdaa3d..947261ca 100644 --- a/src/soc/fu/compunits/test/test_logical_compunit.py +++ b/src/soc/fu/compunits/test/test_logical_compunit.py @@ -1,5 +1,5 @@ import unittest -from soc.decoder.power_enums import (XER_bits, Function) +from openpower.decoder.power_enums import (XER_bits, Function) from soc.fu.logical.test.test_pipe_caller import (LogicalTestCase, get_cu_inputs) diff --git a/src/soc/fu/compunits/test/test_shiftrot_compunit.py b/src/soc/fu/compunits/test/test_shiftrot_compunit.py index 5392ce36..7db830b0 100644 --- a/src/soc/fu/compunits/test/test_shiftrot_compunit.py +++ b/src/soc/fu/compunits/test/test_shiftrot_compunit.py @@ -1,5 +1,5 @@ import unittest -from soc.decoder.power_enums import (XER_bits, Function) +from openpower.decoder.power_enums import (XER_bits, Function) # XXX bad practice: use of global variables from soc.fu.shift_rot.test.test_pipe_caller import get_cu_inputs diff --git a/src/soc/fu/compunits/test/test_spr_compunit.py b/src/soc/fu/compunits/test/test_spr_compunit.py index 11c1ac39..3bdb90ea 100644 --- a/src/soc/fu/compunits/test/test_spr_compunit.py +++ b/src/soc/fu/compunits/test/test_spr_compunit.py @@ -1,5 +1,5 @@ import unittest -from soc.decoder.power_enums import (XER_bits, Function) +from openpower.decoder.power_enums import (XER_bits, Function) from soc.fu.spr.test.test_pipe_caller import get_cu_inputs from soc.fu.spr.test.test_pipe_caller import SPRTestCase # creates the tests diff --git a/src/soc/fu/compunits/test/test_trap_compunit.py b/src/soc/fu/compunits/test/test_trap_compunit.py index 3a6c8dd6..68300ab6 100644 --- a/src/soc/fu/compunits/test/test_trap_compunit.py +++ b/src/soc/fu/compunits/test/test_trap_compunit.py @@ -1,5 +1,5 @@ import unittest -from soc.decoder.power_enums import (XER_bits, Function) +from openpower.decoder.power_enums import (XER_bits, Function) from soc.fu.trap.test.test_pipe_caller import get_cu_inputs from soc.fu.trap.test.test_pipe_caller import TrapTestCase # creates the tests diff --git a/src/soc/fu/cr/cr_input_record.py b/src/soc/fu/cr/cr_input_record.py index 998ca298..7648eb45 100644 --- a/src/soc/fu/cr/cr_input_record.py +++ b/src/soc/fu/cr/cr_input_record.py @@ -1,5 +1,5 @@ from soc.fu.base_input_record import CompOpSubsetBase -from soc.decoder.power_enums import (MicrOp, Function) +from openpower.decoder.power_enums import (MicrOp, Function) class CompCROpSubset(CompOpSubsetBase): diff --git a/src/soc/fu/cr/formal/proof_main_stage.py b/src/soc/fu/cr/formal/proof_main_stage.py index c24fb42c..0a467165 100644 --- a/src/soc/fu/cr/formal/proof_main_stage.py +++ b/src/soc/fu/cr/formal/proof_main_stage.py @@ -14,7 +14,7 @@ from nmigen.cli import rtlil from soc.fu.cr.main_stage import CRMainStage from soc.fu.alu.pipe_data import ALUPipeSpec from soc.fu.alu.alu_input_record import CompALUOpSubset -from soc.decoder.power_enums import MicrOp +from openpower.decoder.power_enums import MicrOp import unittest diff --git a/src/soc/fu/cr/main_stage.py b/src/soc/fu/cr/main_stage.py index c840e32f..5f1edc7a 100644 --- a/src/soc/fu/cr/main_stage.py +++ b/src/soc/fu/cr/main_stage.py @@ -16,10 +16,10 @@ from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array) from nmutil.pipemodbase import PipeModBase from soc.fu.cr.pipe_data import CRInputData, CROutputData -from soc.decoder.power_enums import MicrOp +from openpower.decoder.power_enums import MicrOp -from soc.decoder.power_fields import DecodeFields -from soc.decoder.power_fieldsn import SignalBitRange +from openpower.decoder.power_fields import DecodeFields +from openpower.decoder.power_fieldsn import SignalBitRange class CRMainStage(PipeModBase): diff --git a/src/soc/fu/cr/test/test_pipe_caller.py b/src/soc/fu/cr/test/test_pipe_caller.py index b3b12e1d..ec783718 100644 --- a/src/soc/fu/cr/test/test_pipe_caller.py +++ b/src/soc/fu/cr/test/test_pipe_caller.py @@ -6,13 +6,13 @@ from nmutil.sim_tmp_alternative import Simulator, Settle from nmigen.cli import rtlil import unittest -from soc.decoder.isa.caller import ISACaller, special_sprs -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.decoder.power_enums import (XER_bits, Function) -from soc.decoder.selectable_int import SelectableInt -from soc.simulator.program import Program -from soc.decoder.isa.all import ISA +from openpower.decoder.isa.caller import ISACaller, special_sprs +from openpower.decoder.power_decoder import (create_pdecode) +from openpower.decoder.power_decoder2 import (PowerDecode2) +from openpower.decoder.power_enums import (XER_bits, Function) +from openpower.decoder.selectable_int import SelectableInt +from openpower.simulator.program import Program +from openpower.decoder.isa.all import ISA from soc.config.endian import bigendian from soc.fu.test.common import TestAccumulatorBase, TestCase, ALUHelpers diff --git a/src/soc/fu/div/core_stages.py b/src/soc/fu/div/core_stages.py index fc1d7520..9f63a631 100644 --- a/src/soc/fu/div/core_stages.py +++ b/src/soc/fu/div/core_stages.py @@ -4,10 +4,10 @@ from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array) from nmutil.pipemodbase import PipeModBase from ieee754.part.partsig import PartitionedSignal -from soc.decoder.power_enums import MicrOp +from openpower.decoder.power_enums import MicrOp -from soc.decoder.power_fields import DecodeFields -from soc.decoder.power_fieldsn import SignalBitRange +from openpower.decoder.power_fields import DecodeFields +from openpower.decoder.power_fieldsn import SignalBitRange from soc.fu.div.pipe_data import (CoreInputData, CoreInterstageData, CoreOutputData) diff --git a/src/soc/fu/div/formal/proof_main_stage.py b/src/soc/fu/div/formal/proof_main_stage.py index 5a2c0f8b..997d654d 100644 --- a/src/soc/fu/div/formal/proof_main_stage.py +++ b/src/soc/fu/div/formal/proof_main_stage.py @@ -16,7 +16,7 @@ from nmigen.cli import rtlil from soc.fu.logical.main_stage import LogicalMainStage from soc.fu.alu.pipe_data import ALUPipeSpec from soc.fu.alu.alu_input_record import CompALUOpSubset -from soc.decoder.power_enums import MicrOp +from openpower.decoder.power_enums import MicrOp import unittest diff --git a/src/soc/fu/div/output_stage.py b/src/soc/fu/div/output_stage.py index 92391730..903770dd 100644 --- a/src/soc/fu/div/output_stage.py +++ b/src/soc/fu/div/output_stage.py @@ -9,10 +9,10 @@ from nmutil.pipemodbase import PipeModBase from soc.fu.logical.pipe_data import LogicalInputData from soc.fu.div.pipe_data import DivMulOutputData from ieee754.part.partsig import PartitionedSignal -from soc.decoder.power_enums import MicrOp +from openpower.decoder.power_enums import MicrOp -from soc.decoder.power_fields import DecodeFields -from soc.decoder.power_fieldsn import SignalBitRange +from openpower.decoder.power_fields import DecodeFields +from openpower.decoder.power_fieldsn import SignalBitRange from soc.fu.div.pipe_data import CoreOutputData diff --git a/src/soc/fu/div/setup_stage.py b/src/soc/fu/div/setup_stage.py index 8928f25c..937bcbb0 100644 --- a/src/soc/fu/div/setup_stage.py +++ b/src/soc/fu/div/setup_stage.py @@ -5,10 +5,10 @@ from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array) from nmutil.pipemodbase import PipeModBase from soc.fu.div.pipe_data import DivInputData from ieee754.part.partsig import PartitionedSignal -from soc.decoder.power_enums import MicrOp +from openpower.decoder.power_enums import MicrOp -from soc.decoder.power_fields import DecodeFields -from soc.decoder.power_fieldsn import SignalBitRange +from openpower.decoder.power_fields import DecodeFields +from openpower.decoder.power_fieldsn import SignalBitRange from soc.fu.div.pipe_data import CoreInputData from ieee754.div_rem_sqrt_rsqrt.core import DivPipeCoreOperation from nmutil.util import eq32 diff --git a/src/soc/fu/div/test/helper.py b/src/soc/fu/div/test/helper.py index 5be75e64..7c4f9d69 100644 --- a/src/soc/fu/div/test/helper.py +++ b/src/soc/fu/div/test/helper.py @@ -7,10 +7,10 @@ from nmigen import Module, Signal # Also, check out the cxxsim nmigen branch, and latest yosys from git from nmutil.sim_tmp_alternative import Simulator, Delay -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.decoder.power_enums import XER_bits, Function -from soc.decoder.isa.all import ISA +from openpower.decoder.power_decoder import (create_pdecode) +from openpower.decoder.power_decoder2 import (PowerDecode2) +from openpower.decoder.power_enums import XER_bits, Function +from openpower.decoder.isa.all import ISA from soc.config.endian import bigendian from soc.fu.test.common import ALUHelpers diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py index c636a068..30dc414c 100644 --- a/src/soc/fu/div/test/test_pipe_caller.py +++ b/src/soc/fu/div/test/test_pipe_caller.py @@ -1,6 +1,6 @@ import random import unittest -from soc.simulator.program import Program +from openpower.simulator.program import Program from soc.config.endian import bigendian from soc.fu.test.common import (TestCase, TestAccumulatorBase, skip_case) diff --git a/src/soc/fu/div/test/test_pipe_caller_long.py b/src/soc/fu/div/test/test_pipe_caller_long.py index 5a8d205f..5d2970ca 100644 --- a/src/soc/fu/div/test/test_pipe_caller_long.py +++ b/src/soc/fu/div/test/test_pipe_caller_long.py @@ -1,5 +1,5 @@ import unittest -from soc.simulator.program import Program +from openpower.simulator.program import Program from soc.config.endian import bigendian from soc.fu.test.common import TestAccumulatorBase diff --git a/src/soc/fu/ldst/ldst_input_record.py b/src/soc/fu/ldst/ldst_input_record.py index 57787e46..38fd22cf 100644 --- a/src/soc/fu/ldst/ldst_input_record.py +++ b/src/soc/fu/ldst/ldst_input_record.py @@ -1,7 +1,7 @@ from soc.fu.base_input_record import CompOpSubsetBase from nmigen.hdl.rec import Layout -from soc.decoder.power_enums import MicrOp, Function, LDSTMode +from openpower.decoder.power_enums import MicrOp, Function, LDSTMode class CompLDSTOpSubset(CompOpSubsetBase): diff --git a/src/soc/fu/ldst/test/test_pipe_caller.py b/src/soc/fu/ldst/test/test_pipe_caller.py index 6f489c73..0bffbb1c 100644 --- a/src/soc/fu/ldst/test/test_pipe_caller.py +++ b/src/soc/fu/ldst/test/test_pipe_caller.py @@ -2,13 +2,13 @@ from nmigen import Module, Signal from nmigen.back.pysim import Simulator, Delay, Settle from nmigen.cli import rtlil import unittest -from soc.decoder.isa.caller import special_sprs -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn) -from soc.decoder.selectable_int import SelectableInt -from soc.simulator.program import Program -from soc.decoder.isa.all import ISA +from openpower.decoder.isa.caller import special_sprs +from openpower.decoder.power_decoder import (create_pdecode) +from openpower.decoder.power_decoder2 import (PowerDecode2) +from openpower.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn) +from openpower.decoder.selectable_int import SelectableInt +from openpower.simulator.program import Program +from openpower.decoder.isa.all import ISA from soc.config.endian import bigendian diff --git a/src/soc/fu/logical/formal/proof_input_stage.py b/src/soc/fu/logical/formal/proof_input_stage.py index ed0c7511..d11f832d 100644 --- a/src/soc/fu/logical/formal/proof_input_stage.py +++ b/src/soc/fu/logical/formal/proof_input_stage.py @@ -9,7 +9,7 @@ from nmigen.cli import rtlil from soc.fu.alu.input_stage import ALUInputStage from soc.fu.alu.pipe_data import ALUPipeSpec from soc.fu.alu.alu_input_record import CompALUOpSubset -from soc.decoder.power_enums import MicrOp +from openpower.decoder.power_enums import MicrOp import unittest diff --git a/src/soc/fu/logical/formal/proof_main_stage.py b/src/soc/fu/logical/formal/proof_main_stage.py index e7cf254a..179d9ba2 100644 --- a/src/soc/fu/logical/formal/proof_main_stage.py +++ b/src/soc/fu/logical/formal/proof_main_stage.py @@ -16,7 +16,7 @@ from nmigen.cli import rtlil from soc.fu.logical.main_stage import LogicalMainStage from soc.fu.alu.pipe_data import ALUPipeSpec from soc.fu.alu.alu_input_record import CompALUOpSubset -from soc.decoder.power_enums import MicrOp +from openpower.decoder.power_enums import MicrOp import unittest diff --git a/src/soc/fu/logical/logical_input_record.py b/src/soc/fu/logical/logical_input_record.py index 811823df..b6ea9287 100644 --- a/src/soc/fu/logical/logical_input_record.py +++ b/src/soc/fu/logical/logical_input_record.py @@ -1,5 +1,5 @@ from nmigen.hdl.rec import Layout -from soc.decoder.power_enums import MicrOp, Function, CryIn +from openpower.decoder.power_enums import MicrOp, Function, CryIn from soc.fu.base_input_record import CompOpSubsetBase diff --git a/src/soc/fu/logical/main_stage.py b/src/soc/fu/logical/main_stage.py index c9cc4c86..e56f3445 100644 --- a/src/soc/fu/logical/main_stage.py +++ b/src/soc/fu/logical/main_stage.py @@ -14,10 +14,10 @@ from soc.fu.logical.bpermd import Bpermd from soc.fu.logical.popcount import Popcount from soc.fu.logical.pipe_data import LogicalOutputData from ieee754.part.partsig import PartitionedSignal -from soc.decoder.power_enums import MicrOp +from openpower.decoder.power_enums import MicrOp -from soc.decoder.power_fields import DecodeFields -from soc.decoder.power_fieldsn import SignalBitRange +from openpower.decoder.power_fields import DecodeFields +from openpower.decoder.power_fieldsn import SignalBitRange class LogicalMainStage(PipeModBase): diff --git a/src/soc/fu/logical/output_stage.py b/src/soc/fu/logical/output_stage.py index 4a6694a8..73b48d1e 100644 --- a/src/soc/fu/logical/output_stage.py +++ b/src/soc/fu/logical/output_stage.py @@ -7,7 +7,7 @@ from soc.fu.common_output_stage import CommonOutputStage from soc.fu.logical.pipe_data import (LogicalInputData, LogicalOutputData, LogicalOutputDataFinal) from ieee754.part.partsig import PartitionedSignal -from soc.decoder.power_enums import MicrOp +from openpower.decoder.power_enums import MicrOp class LogicalOutputStage(CommonOutputStage): diff --git a/src/soc/fu/logical/test/test_pipe_caller.py b/src/soc/fu/logical/test/test_pipe_caller.py index 8508a4a2..a6b87e3e 100644 --- a/src/soc/fu/logical/test/test_pipe_caller.py +++ b/src/soc/fu/logical/test/test_pipe_caller.py @@ -7,13 +7,13 @@ from nmutil.sim_tmp_alternative import Simulator, Settle from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil import unittest -from soc.decoder.isa.caller import ISACaller, special_sprs -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.decoder.power_enums import (XER_bits, Function) -from soc.decoder.selectable_int import SelectableInt -from soc.simulator.program import Program -from soc.decoder.isa.all import ISA +from openpower.decoder.isa.caller import ISACaller, special_sprs +from openpower.decoder.power_decoder import (create_pdecode) +from openpower.decoder.power_decoder2 import (PowerDecode2) +from openpower.decoder.power_enums import (XER_bits, Function) +from openpower.decoder.selectable_int import SelectableInt +from openpower.simulator.program import Program +from openpower.decoder.isa.all import ISA from soc.config.endian import bigendian diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py index 76cff311..76dec27a 100644 --- a/src/soc/fu/mmu/fsm.py +++ b/src/soc/fu/mmu/fsm.py @@ -7,10 +7,10 @@ from nmutil.util import rising_edge from soc.experiment.mmu import MMU from soc.experiment.dcache import DCache -from soc.decoder.power_fields import DecodeFields -from soc.decoder.power_fieldsn import SignalBitRange -from soc.decoder.power_decoder2 import decode_spr_num -from soc.decoder.power_enums import MicrOp, XER_bits +from openpower.decoder.power_fields import DecodeFields +from openpower.decoder.power_fieldsn import SignalBitRange +from openpower.decoder.power_decoder2 import decode_spr_num +from openpower.decoder.power_enums import MicrOp, XER_bits from soc.experiment.pimem import PortInterface from soc.experiment.pimem import PortInterfaceBase diff --git a/src/soc/fu/mmu/mmu_input_record.py b/src/soc/fu/mmu/mmu_input_record.py index f063e2ea..602fbab7 100644 --- a/src/soc/fu/mmu/mmu_input_record.py +++ b/src/soc/fu/mmu/mmu_input_record.py @@ -1,5 +1,5 @@ from soc.fu.base_input_record import CompOpSubsetBase -from soc.decoder.power_enums import (MicrOp, Function) +from openpower.decoder.power_enums import (MicrOp, Function) class CompMMUOpSubset(CompOpSubsetBase): diff --git a/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py b/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py index 5037ceba..599b69a8 100644 --- a/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py +++ b/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py @@ -1,6 +1,6 @@ from nmigen import Module, Signal from soc.simple.test.test_issuer import TestRunner -from soc.simulator.program import Program +from openpower.simulator.program import Program from soc.config.endian import bigendian import unittest diff --git a/src/soc/fu/mmu/test/test_issuer_mmu_rom.py b/src/soc/fu/mmu/test/test_issuer_mmu_rom.py index 2552b14b..f1a80fc7 100644 --- a/src/soc/fu/mmu/test/test_issuer_mmu_rom.py +++ b/src/soc/fu/mmu/test/test_issuer_mmu_rom.py @@ -1,6 +1,6 @@ from nmigen import Module, Signal from soc.simple.test.test_runner import TestRunner -from soc.simulator.program import Program +from openpower.simulator.program import Program from soc.config.endian import bigendian import unittest diff --git a/src/soc/fu/mmu/test/test_non_production_core.py b/src/soc/fu/mmu/test/test_non_production_core.py index f9f873e2..ee01ca5b 100644 --- a/src/soc/fu/mmu/test/test_non_production_core.py +++ b/src/soc/fu/mmu/test/test_non_production_core.py @@ -4,13 +4,13 @@ from nmutil.sim_tmp_alternative import Simulator, Settle from nmigen.cli import rtlil import unittest -from soc.decoder.isa.caller import ISACaller, special_sprs -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn) -from soc.decoder.selectable_int import SelectableInt -from soc.simulator.program import Program -from soc.decoder.isa.all import ISA +from openpower.decoder.isa.caller import ISACaller, special_sprs +from openpower.decoder.power_decoder import (create_pdecode) +from openpower.decoder.power_decoder2 import (PowerDecode2) +from openpower.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn) +from openpower.decoder.selectable_int import SelectableInt +from openpower.simulator.program import Program +from openpower.decoder.isa.all import ISA from soc.config.endian import bigendian from soc.consts import MSR diff --git a/src/soc/fu/mmu/test/test_pipe_caller.py b/src/soc/fu/mmu/test/test_pipe_caller.py index e45b3065..df489dbc 100644 --- a/src/soc/fu/mmu/test/test_pipe_caller.py +++ b/src/soc/fu/mmu/test/test_pipe_caller.py @@ -6,13 +6,13 @@ from nmutil.sim_tmp_alternative import Simulator, Settle from nmigen.cli import rtlil import unittest -from soc.decoder.isa.caller import ISACaller, special_sprs -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn) -from soc.decoder.selectable_int import SelectableInt -from soc.simulator.program import Program -from soc.decoder.isa.all import ISA +from openpower.decoder.isa.caller import ISACaller, special_sprs +from openpower.decoder.power_decoder import (create_pdecode) +from openpower.decoder.power_decoder2 import (PowerDecode2) +from openpower.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn) +from openpower.decoder.selectable_int import SelectableInt +from openpower.simulator.program import Program +from openpower.decoder.isa.all import ISA from soc.config.endian import bigendian from soc.consts import MSR diff --git a/src/soc/fu/mul/formal/proof_main_stage.py b/src/soc/fu/mul/formal/proof_main_stage.py index 0cf767f3..f1837baa 100644 --- a/src/soc/fu/mul/formal/proof_main_stage.py +++ b/src/soc/fu/mul/formal/proof_main_stage.py @@ -49,15 +49,15 @@ from nmutil.formaltest import FHDLTestCase from nmutil.stageapi import StageChain from nmigen.cli import rtlil -from soc.decoder.power_fields import DecodeFields -from soc.decoder.power_fieldsn import SignalBitRange +from openpower.decoder.power_fields import DecodeFields +from openpower.decoder.power_fieldsn import SignalBitRange from soc.fu.mul.pipe_data import CompMULOpSubset, MulPipeSpec from soc.fu.mul.pre_stage import MulMainStage1 from soc.fu.mul.main_stage import MulMainStage2 from soc.fu.mul.post_stage import MulMainStage3 -from soc.decoder.power_enums import MicrOp +from openpower.decoder.power_enums import MicrOp import unittest diff --git a/src/soc/fu/mul/mul_input_record.py b/src/soc/fu/mul/mul_input_record.py index 1f321cbd..a4904464 100644 --- a/src/soc/fu/mul/mul_input_record.py +++ b/src/soc/fu/mul/mul_input_record.py @@ -1,7 +1,7 @@ from soc.fu.base_input_record import CompOpSubsetBase from nmigen.hdl.rec import Layout -from soc.decoder.power_enums import MicrOp, Function, CryIn +from openpower.decoder.power_enums import MicrOp, Function, CryIn class CompMULOpSubset(CompOpSubsetBase): diff --git a/src/soc/fu/mul/post_stage.py b/src/soc/fu/mul/post_stage.py index 14d2d911..0b45c791 100644 --- a/src/soc/fu/mul/post_stage.py +++ b/src/soc/fu/mul/post_stage.py @@ -11,7 +11,7 @@ from nmutil.pipemodbase import PipeModBase from soc.fu.div.pipe_data import DivMulOutputData from soc.fu.mul.pipe_data import MulOutputData from ieee754.part.partsig import PartitionedSignal -from soc.decoder.power_enums import MicrOp +from openpower.decoder.power_enums import MicrOp class MulMainStage3(PipeModBase): diff --git a/src/soc/fu/mul/test/helper.py b/src/soc/fu/mul/test/helper.py index a0099318..140dd8fb 100644 --- a/src/soc/fu/mul/test/helper.py +++ b/src/soc/fu/mul/test/helper.py @@ -8,13 +8,13 @@ import power_instruction_analyzer as pia from nmigen.cli import rtlil import unittest -from soc.decoder.isa.caller import ISACaller, special_sprs -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn) -from soc.decoder.selectable_int import SelectableInt -from soc.simulator.program import Program -from soc.decoder.isa.all import ISA +from openpower.decoder.isa.caller import ISACaller, special_sprs +from openpower.decoder.power_decoder import (create_pdecode) +from openpower.decoder.power_decoder2 import (PowerDecode2) +from openpower.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn) +from openpower.decoder.selectable_int import SelectableInt +from openpower.simulator.program import Program +from openpower.decoder.isa.all import ISA from soc.config.endian import bigendian from soc.fu.test.common import (TestAccumulatorBase, TestCase, ALUHelpers) diff --git a/src/soc/fu/mul/test/test_pipe_caller.py b/src/soc/fu/mul/test/test_pipe_caller.py index 36e5faf4..e4f27f33 100644 --- a/src/soc/fu/mul/test/test_pipe_caller.py +++ b/src/soc/fu/mul/test/test_pipe_caller.py @@ -1,6 +1,6 @@ import unittest from soc.fu.mul.test.helper import MulTestHelper -from soc.simulator.program import Program +from openpower.simulator.program import Program from soc.config.endian import bigendian from soc.fu.test.common import TestAccumulatorBase, skip_case diff --git a/src/soc/fu/mul/test/test_pipe_caller_long.py b/src/soc/fu/mul/test/test_pipe_caller_long.py index d1363612..56d8795a 100644 --- a/src/soc/fu/mul/test/test_pipe_caller_long.py +++ b/src/soc/fu/mul/test/test_pipe_caller_long.py @@ -1,6 +1,6 @@ import unittest from soc.fu.mul.test.helper import MulTestHelper -from soc.simulator.program import Program +from openpower.simulator.program import Program from soc.config.endian import bigendian from soc.fu.test.common import (TestAccumulatorBase) import random diff --git a/src/soc/fu/pipe_data.py b/src/soc/fu/pipe_data.py index e944e868..a9318eb5 100644 --- a/src/soc/fu/pipe_data.py +++ b/src/soc/fu/pipe_data.py @@ -1,7 +1,7 @@ from nmutil.concurrentunit import PipeContext from nmutil.dynamicpipe import SimpleHandshakeRedir from nmigen import Signal -from soc.decoder.power_decoder2 import Data +from openpower.decoder.power_decoder2 import Data from soc.fu.regspec import get_regspec_bitwidth diff --git a/src/soc/fu/shift_rot/formal/proof_main_stage.py b/src/soc/fu/shift_rot/formal/proof_main_stage.py index 8e5f9ecd..dde891ec 100644 --- a/src/soc/fu/shift_rot/formal/proof_main_stage.py +++ b/src/soc/fu/shift_rot/formal/proof_main_stage.py @@ -15,7 +15,7 @@ from soc.fu.shift_rot.main_stage import ShiftRotMainStage from soc.fu.shift_rot.rotator import right_mask, left_mask from soc.fu.shift_rot.pipe_data import ShiftRotPipeSpec from soc.fu.shift_rot.sr_input_record import CompSROpSubset -from soc.decoder.power_enums import MicrOp +from openpower.decoder.power_enums import MicrOp from soc.consts import field import unittest diff --git a/src/soc/fu/shift_rot/main_stage.py b/src/soc/fu/shift_rot/main_stage.py index 1e4b8b1a..0be12d1b 100644 --- a/src/soc/fu/shift_rot/main_stage.py +++ b/src/soc/fu/shift_rot/main_stage.py @@ -11,11 +11,11 @@ from nmutil.pipemodbase import PipeModBase from soc.fu.shift_rot.pipe_data import (ShiftRotOutputData, ShiftRotInputData) from ieee754.part.partsig import PartitionedSignal -from soc.decoder.power_enums import MicrOp +from openpower.decoder.power_enums import MicrOp from soc.fu.shift_rot.rotator import Rotator -from soc.decoder.power_fields import DecodeFields -from soc.decoder.power_fieldsn import SignalBitRange +from openpower.decoder.power_fields import DecodeFields +from openpower.decoder.power_fieldsn import SignalBitRange class ShiftRotMainStage(PipeModBase): diff --git a/src/soc/fu/shift_rot/sr_input_record.py b/src/soc/fu/shift_rot/sr_input_record.py index 18698a62..94cbad06 100644 --- a/src/soc/fu/shift_rot/sr_input_record.py +++ b/src/soc/fu/shift_rot/sr_input_record.py @@ -1,7 +1,7 @@ from soc.fu.base_input_record import CompOpSubsetBase from nmigen.hdl.rec import Layout -from soc.decoder.power_enums import MicrOp, Function, CryIn +from openpower.decoder.power_enums import MicrOp, Function, CryIn class CompSROpSubset(CompOpSubsetBase): diff --git a/src/soc/fu/shift_rot/test/test_maskgen.py b/src/soc/fu/shift_rot/test/test_maskgen.py index 385899d1..27a1d4c4 100644 --- a/src/soc/fu/shift_rot/test/test_maskgen.py +++ b/src/soc/fu/shift_rot/test/test_maskgen.py @@ -3,7 +3,7 @@ from nmigen.back.pysim import Simulator, Delay, Settle from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil from soc.fu.shift_rot.maskgen import MaskGen -from soc.decoder.helpers import MASK +from openpower.decoder.helpers import MASK import random import unittest diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py index de7f9c06..fae3d029 100644 --- a/src/soc/fu/shift_rot/test/test_pipe_caller.py +++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py @@ -4,13 +4,13 @@ from soc.fu.alu.alu_input_record import CompALUOpSubset from soc.fu.shift_rot.pipeline import ShiftRotBasePipe from soc.fu.test.common import TestAccumulatorBase, TestCase, ALUHelpers from soc.config.endian import bigendian -from soc.decoder.isa.all import ISA -from soc.simulator.program import Program -from soc.decoder.selectable_int import SelectableInt -from soc.decoder.power_enums import (XER_bits, Function, CryIn) -from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.isa.caller import ISACaller, special_sprs +from openpower.decoder.isa.all import ISA +from openpower.simulator.program import Program +from openpower.decoder.selectable_int import SelectableInt +from openpower.decoder.power_enums import (XER_bits, Function, CryIn) +from openpower.decoder.power_decoder2 import (PowerDecode2) +from openpower.decoder.power_decoder import (create_pdecode) +from openpower.decoder.isa.caller import ISACaller, special_sprs import unittest from nmigen.cli import rtlil from nmigen import Module, Signal diff --git a/src/soc/fu/spr/formal/proof_main_stage.py b/src/soc/fu/spr/formal/proof_main_stage.py index 2c712115..1431a038 100644 --- a/src/soc/fu/spr/formal/proof_main_stage.py +++ b/src/soc/fu/spr/formal/proof_main_stage.py @@ -18,10 +18,10 @@ from soc.fu.spr.main_stage import SPRMainStage from soc.fu.spr.pipe_data import SPRPipeSpec from soc.fu.spr.spr_input_record import CompSPROpSubset -from soc.decoder.power_decoder2 import decode_spr_num -from soc.decoder.power_enums import MicrOp, SPR, XER_bits -from soc.decoder.power_fields import DecodeFields -from soc.decoder.power_fieldsn import SignalBitRange +from openpower.decoder.power_decoder2 import decode_spr_num +from openpower.decoder.power_enums import MicrOp, SPR, XER_bits +from openpower.decoder.power_fields import DecodeFields +from openpower.decoder.power_fieldsn import SignalBitRange # use POWER numbering. sigh. def xer_bit(name): diff --git a/src/soc/fu/spr/main_stage.py b/src/soc/fu/spr/main_stage.py index cca0c24e..6d9d13a6 100644 --- a/src/soc/fu/spr/main_stage.py +++ b/src/soc/fu/spr/main_stage.py @@ -7,11 +7,11 @@ from nmigen import (Module, Signal, Cat) from nmutil.pipemodbase import PipeModBase from soc.fu.spr.pipe_data import SPRInputData, SPROutputData -from soc.decoder.power_enums import MicrOp, SPRfull, SPRreduced, XER_bits +from openpower.decoder.power_enums import MicrOp, SPRfull, SPRreduced, XER_bits -from soc.decoder.power_fields import DecodeFields -from soc.decoder.power_fieldsn import SignalBitRange -from soc.decoder.power_decoder2 import decode_spr_num +from openpower.decoder.power_fields import DecodeFields +from openpower.decoder.power_fieldsn import SignalBitRange +from openpower.decoder.power_decoder2 import decode_spr_num class SPRMainStage(PipeModBase): diff --git a/src/soc/fu/spr/spr_input_record.py b/src/soc/fu/spr/spr_input_record.py index a19d2ba3..4440e71e 100644 --- a/src/soc/fu/spr/spr_input_record.py +++ b/src/soc/fu/spr/spr_input_record.py @@ -1,5 +1,5 @@ from soc.fu.base_input_record import CompOpSubsetBase -from soc.decoder.power_enums import (MicrOp, Function) +from openpower.decoder.power_enums import (MicrOp, Function) class CompSPROpSubset(CompOpSubsetBase): diff --git a/src/soc/fu/spr/test/test_pipe_caller.py b/src/soc/fu/spr/test/test_pipe_caller.py index f2bc03c7..87ba83ca 100644 --- a/src/soc/fu/spr/test/test_pipe_caller.py +++ b/src/soc/fu/spr/test/test_pipe_caller.py @@ -6,13 +6,13 @@ from nmutil.sim_tmp_alternative import Simulator, Settle from nmigen.cli import rtlil import unittest -from soc.decoder.isa.caller import ISACaller, special_sprs -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn) -from soc.decoder.selectable_int import SelectableInt -from soc.simulator.program import Program -from soc.decoder.isa.all import ISA +from openpower.decoder.isa.caller import ISACaller, special_sprs +from openpower.decoder.power_decoder import (create_pdecode) +from openpower.decoder.power_decoder2 import (PowerDecode2) +from openpower.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn) +from openpower.decoder.selectable_int import SelectableInt +from openpower.simulator.program import Program +from openpower.decoder.isa.all import ISA from soc.config.endian import bigendian from soc.consts import MSR diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py index c21ebd7f..359c7d6d 100644 --- a/src/soc/fu/test/common.py +++ b/src/soc/fu/test/common.py @@ -6,7 +6,7 @@ Bugreports: import inspect import functools import types -from soc.decoder.power_enums import XER_bits, CryIn, spr_dict +from openpower.decoder.power_enums import XER_bits, CryIn, spr_dict from soc.regfile.util import fast_reg_to_spr, slow_reg_to_spr # HACK! from soc.regfile.regfiles import XERRegs, FastRegs diff --git a/src/soc/fu/trap/formal/proof_main_stage.py b/src/soc/fu/trap/formal/proof_main_stage.py index 85d1abd9..c88c0ac2 100644 --- a/src/soc/fu/trap/formal/proof_main_stage.py +++ b/src/soc/fu/trap/formal/proof_main_stage.py @@ -21,7 +21,7 @@ from nmutil.formaltest import FHDLTestCase from soc.consts import MSR, MSRb, PI, TT, field -from soc.decoder.power_enums import MicrOp +from openpower.decoder.power_enums import MicrOp from soc.fu.trap.main_stage import TrapMainStage from soc.fu.trap.pipe_data import TrapPipeSpec diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py index 95dabe7f..5b272e63 100644 --- a/src/soc/fu/trap/main_stage.py +++ b/src/soc/fu/trap/main_stage.py @@ -14,11 +14,11 @@ from nmutil.pipemodbase import PipeModBase from nmutil.extend import exts from soc.fu.trap.pipe_data import TrapInputData, TrapOutputData from soc.fu.branch.main_stage import br_ext -from soc.decoder.power_enums import MicrOp +from openpower.decoder.power_enums import MicrOp from soc.experiment.mem_types import LDSTException -from soc.decoder.power_fields import DecodeFields -from soc.decoder.power_fieldsn import SignalBitRange +from openpower.decoder.power_fields import DecodeFields +from openpower.decoder.power_fieldsn import SignalBitRange from soc.consts import MSR, PI, TT, field, field_slice diff --git a/src/soc/fu/trap/test/test_pipe_caller.py b/src/soc/fu/trap/test/test_pipe_caller.py index ed9d72d2..f9fa09ce 100644 --- a/src/soc/fu/trap/test/test_pipe_caller.py +++ b/src/soc/fu/trap/test/test_pipe_caller.py @@ -7,13 +7,13 @@ from nmutil.sim_tmp_alternative import Simulator, Settle from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil import unittest -from soc.decoder.isa.caller import ISACaller, special_sprs -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn) -from soc.decoder.selectable_int import SelectableInt -from soc.simulator.program import Program -from soc.decoder.isa.all import ISA +from openpower.decoder.isa.caller import ISACaller, special_sprs +from openpower.decoder.power_decoder import (create_pdecode) +from openpower.decoder.power_decoder2 import (PowerDecode2) +from openpower.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn) +from openpower.decoder.selectable_int import SelectableInt +from openpower.simulator.program import Program +from openpower.decoder.isa.all import ISA from soc.config.endian import bigendian from soc.consts import MSR diff --git a/src/soc/fu/trap/trap_input_record.py b/src/soc/fu/trap/trap_input_record.py index 44fd5d6b..0d08f5ec 100644 --- a/src/soc/fu/trap/trap_input_record.py +++ b/src/soc/fu/trap/trap_input_record.py @@ -1,5 +1,5 @@ from soc.fu.base_input_record import CompOpSubsetBase -from soc.decoder.power_enums import (MicrOp, Function) +from openpower.decoder.power_enums import (MicrOp, Function) from soc.consts import TT from soc.experiment.mem_types import LDSTException diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py index 167ae511..82019a25 100644 --- a/src/soc/regfile/regfiles.py +++ b/src/soc/regfile/regfiles.py @@ -26,7 +26,7 @@ Links: from soc.regfile.regfile import RegFile, RegFileArray, RegFileMem from soc.regfile.virtual_port import VirtualRegPort -from soc.decoder.power_enums import SPRfull, SPRreduced +from openpower.decoder.power_enums import SPRfull, SPRreduced # "State" Regfile diff --git a/src/soc/regfile/util.py b/src/soc/regfile/util.py index e5f095dc..7f4e8778 100644 --- a/src/soc/regfile/util.py +++ b/src/soc/regfile/util.py @@ -1,5 +1,5 @@ from soc.regfile.regfiles import FastRegs -from soc.decoder.power_enums import SPRfull as SPR, spr_dict +from openpower.decoder.power_enums import SPRfull as SPR, spr_dict # note that we can get away with using SPRfull here because the values # (numerical values) are what is used for lookup. diff --git a/src/soc/scoreboard/instruction_q.py b/src/soc/scoreboard/instruction_q.py index 4dec3cf2..9c3d58d8 100644 --- a/src/soc/scoreboard/instruction_q.py +++ b/src/soc/scoreboard/instruction_q.py @@ -6,7 +6,7 @@ from nmigen import Module, Signal, Cat, Array, Const, Repl, Elaboratable from nmutil.iocontrol import RecordObject from nmutil.nmoperator import eq, shape, cat -from soc.decoder.power_decoder2 import Decode2ToExecute1Type +from openpower.decoder.power_decoder2 import Decode2ToExecute1Type class Instruction(Decode2ToExecute1Type): diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index 215bcaab..f4cf959d 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -22,22 +22,22 @@ before allowing a new instruction to proceed. from nmigen import Elaboratable, Module, Signal, ResetSignal, Cat, Mux from nmigen.cli import rtlil -from soc.decoder.power_decoder2 import PowerDecodeSubset -from soc.decoder.power_regspec_map import regspec_decode_read -from soc.decoder.power_regspec_map import regspec_decode_write +from openpower.decoder.power_decoder2 import PowerDecodeSubset +from openpower.decoder.power_regspec_map import regspec_decode_read +from openpower.decoder.power_regspec_map import regspec_decode_write from nmutil.picker import PriorityPicker from nmutil.util import treereduce from soc.fu.compunits.compunits import AllFunctionUnits from soc.regfile.regfiles import RegFiles -from soc.decoder.decode2execute1 import Decode2ToExecute1Type -from soc.decoder.decode2execute1 import IssuerDecode2ToOperand -from soc.decoder.power_decoder2 import get_rdflags -from soc.decoder.decode2execute1 import Data +from openpower.decoder.decode2execute1 import Decode2ToExecute1Type +from openpower.decoder.decode2execute1 import IssuerDecode2ToOperand +from openpower.decoder.power_decoder2 import get_rdflags +from openpower.decoder.decode2execute1 import Data from soc.experiment.l0_cache import TstL0CacheBuffer # test only from soc.config.test.test_loadstore import TestMemPspec -from soc.decoder.power_enums import MicrOp +from openpower.decoder.power_enums import MicrOp from soc.config.state import CoreState import operator diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index d2c248d5..4afa0d7a 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -23,16 +23,16 @@ import sys from nmigen.lib.coding import PriorityEncoder -from soc.decoder.power_decoder import create_pdecode -from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder -from soc.decoder.decode2execute1 import IssuerDecode2ToOperand -from soc.decoder.decode2execute1 import Data +from openpower.decoder.power_decoder import create_pdecode +from openpower.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder +from openpower.decoder.decode2execute1 import IssuerDecode2ToOperand +from openpower.decoder.decode2execute1 import Data from soc.experiment.testmem import TestMemory # test only for instructions from soc.regfile.regfiles import StateRegs, FastRegs from soc.simple.core import NonProductionCore from soc.config.test.test_loadstore import TestMemPspec from soc.config.ifetch import ConfigFetchUnit -from soc.decoder.power_enums import (MicrOp, SVP64PredInt, SVP64PredCR, +from openpower.decoder.power_enums import (MicrOp, SVP64PredInt, SVP64PredCR, SVP64PredMode) from soc.consts import (CR, SVP64CROffs) from soc.debug.dmi import CoreDebug, DMIInterface @@ -399,7 +399,7 @@ class TestIssuerInternal(Elaboratable): be done through multiple reads, extracting one relevant at a time. later, a faster way would be to use the 32-bit-wide CR port but this is more complex decoding, here. equivalent code used in - ISACaller is "from soc.decoder.isa.caller import get_predcr" + ISACaller is "from openpower.decoder.isa.caller import get_predcr" note: this ENTIRE FSM is not to be called when svp64 is disabled """ diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py index f25d250c..67490101 100644 --- a/src/soc/simple/test/test_core.py +++ b/src/soc/simple/test/test_core.py @@ -9,16 +9,16 @@ from nmigen.back.pysim import Simulator, Delay, Settle from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil import unittest -from soc.decoder.isa.caller import special_sprs -from soc.decoder.power_decoder import create_pdecode -from soc.decoder.power_decoder2 import PowerDecode2 -from soc.decoder.selectable_int import SelectableInt -from soc.decoder.isa.all import ISA +from openpower.decoder.isa.caller import special_sprs +from openpower.decoder.power_decoder import create_pdecode +from openpower.decoder.power_decoder2 import PowerDecode2 +from openpower.decoder.selectable_int import SelectableInt +from openpower.decoder.isa.all import ISA # note that for testing using SPRfull should be ok here -from soc.decoder.power_enums import SPRfull as SPR, spr_dict, Function, XER_bits +from openpower.decoder.power_enums import SPRfull as SPR, spr_dict, Function, XER_bits from soc.config.test.test_loadstore import TestMemPspec -from soc.config.endian import bigendian +from openpower.endian import bigendian from soc.simple.core import NonProductionCore from soc.experiment.compalu_multi import find_ok # hack diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py index 3170cfbb..92a69ae2 100644 --- a/src/soc/simple/test/test_issuer.py +++ b/src/soc/simple/test/test_issuer.py @@ -21,8 +21,8 @@ from soc.fu.cr.test.test_pipe_caller import CRTestCase # from soc.fu.branch.test.test_pipe_caller import BranchTestCase # from soc.fu.spr.test.test_pipe_caller import SPRTestCase from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase -from soc.simulator.test_sim import (GeneralTestCases, AttnTestCase) -# from soc.simulator.test_helloworld_sim import HelloTestCases +from openpower.simulator.test_sim import (GeneralTestCases, AttnTestCase) +# from openpower.simulator.test_helloworld_sim import HelloTestCases if __name__ == "__main__": diff --git a/src/soc/simple/test/test_microwatt.py b/src/soc/simple/test/test_microwatt.py index c666a815..a7af8328 100644 --- a/src/soc/simple/test/test_microwatt.py +++ b/src/soc/simple/test/test_microwatt.py @@ -1,4 +1,4 @@ -from soc.simulator.program import Program +from openpower.simulator.program import Program from soc.fu.test.common import TestCase import unittest @@ -8,7 +8,7 @@ from nmigen.back.pysim import Simulator, Delay, Settle from nmutil.formaltest import FHDLTestCase from soc.simple.issuer import TestIssuer -from soc.config.endian import bigendian +from openpower.endian import bigendian from soc.config.test.test_loadstore import TestMemPspec diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py index 2cfd60ee..85a14869 100644 --- a/src/soc/simple/test/test_runner.py +++ b/src/soc/simple/test/test_runner.py @@ -13,12 +13,12 @@ from nmutil.sim_tmp_alternative import Simulator, Settle from nmutil.formaltest import FHDLTestCase from nmutil.gtkw import write_gtkw from nmigen.cli import rtlil -from soc.decoder.isa.caller import special_sprs, SVP64State -from soc.decoder.isa.all import ISA -from soc.config.endian import bigendian +from openpower.decoder.isa.caller import special_sprs, SVP64State +from openpower.decoder.isa.all import ISA +from openpower.endian import bigendian -from soc.decoder.power_decoder import create_pdecode -from soc.decoder.power_decoder2 import PowerDecode2 +from openpower.decoder.power_decoder import create_pdecode +from openpower.decoder.power_decoder2 import PowerDecode2 from soc.regfile.regfiles import StateRegs from soc.simple.issuer import TestIssuerInternal diff --git a/src/soc/sv/trans/svp64.py b/src/soc/sv/trans/svp64.py index 5df66ce1..e8f592fb 100644 --- a/src/soc/sv/trans/svp64.py +++ b/src/soc/sv/trans/svp64.py @@ -17,7 +17,7 @@ Bugtracker: https://bugs.libre-soc.org/show_bug.cgi?id=578 import os, sys from collections import OrderedDict -from soc.decoder.isa.caller import (SVP64PrefixFields, SV64P_MAJOR_SIZE, +from openpower.decoder.isa.caller import (SVP64PrefixFields, SV64P_MAJOR_SIZE, SV64P_PID_SIZE, SVP64RMFields, SVP64RM_EXTRA2_SPEC_SIZE, SVP64RM_EXTRA3_SPEC_SIZE, @@ -25,9 +25,9 @@ from soc.decoder.isa.caller import (SVP64PrefixFields, SV64P_MAJOR_SIZE, SVP64RM_MMODE_SIZE, SVP64RM_MASK_SIZE, SVP64RM_SUBVL_SIZE, SVP64RM_EWSRC_SIZE, SVP64RM_ELWIDTH_SIZE) -from soc.decoder.pseudo.pagereader import ISA -from soc.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra -from soc.decoder.selectable_int import SelectableInt +from openpower.decoder.pseudo.pagereader import ISA +from openpower.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra +from openpower.decoder.selectable_int import SelectableInt from soc.consts import SVP64MODE -- 2.30.2