From 00154110309c7c47286165aaa809ea3fc199e516 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 10 Nov 2018 20:24:59 +0000 Subject: [PATCH] remove extra rv_sl and rv_sr overload fns --- riscv/insns/c_lui.h | 2 +- riscv/insns/c_srai.h | 2 +- riscv/insns/c_srli.h | 2 +- riscv/sv_insn_redirect.cc | 10 ---------- riscv/sv_insn_redirect.h | 2 -- 5 files changed, 3 insertions(+), 15 deletions(-) diff --git a/riscv/insns/c_lui.h b/riscv/insns/c_lui.h index dcbc91d..1f38222 100644 --- a/riscv/insns/c_lui.h +++ b/riscv/insns/c_lui.h @@ -4,5 +4,5 @@ if (insn.insn_t::rvc_rd() == 2) { // c.addi16sp WRITE_REG({X_SP,0}, sext_xlen(rv_add(RVC_SP, insn.rvc_addi16sp_imm()))); } else { require(rv_ne(insn.rvc_imm(), sv_reg_t(0L))); - WRITE_RD(rv_sl(insn.rvc_imm(), sv_reg_t(12UL))); + WRITE_RD(rv_sl(insn.rvc_imm(), sv_reg_t(12UL), xlen)); } diff --git a/riscv/insns/c_srai.h b/riscv/insns/c_srai.h index 9d67625..6349ccc 100644 --- a/riscv/insns/c_srai.h +++ b/riscv/insns/c_srai.h @@ -1,3 +1,3 @@ require_extension('C'); require(rv_lt(insn.rvc_zimm(), sv_reg_t(xlen))); -WRITE_RVC_RS1S(sext_xlen(rv_sr(sext_xlen(RVC_RS1S), insn.rvc_zimm()))); +WRITE_RVC_RS1S(sext_xlen(rv_sr(sext_xlen(RVC_RS1S), insn.rvc_zimm(), xlen))); diff --git a/riscv/insns/c_srli.h b/riscv/insns/c_srli.h index 7cb790f..9d39677 100644 --- a/riscv/insns/c_srli.h +++ b/riscv/insns/c_srli.h @@ -1,3 +1,3 @@ require_extension('C'); require(rv_lt(insn.rvc_zimm(), sv_reg_t(xlen))); -WRITE_RVC_RS1S(sext_xlen(rv_sr(zext_xlen(RVC_RS1S), insn.rvc_zimm()))); +WRITE_RVC_RS1S(sext_xlen(rv_sr(zext_xlen(RVC_RS1S), insn.rvc_zimm(), xlen))); diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc index f5fbb0d..0a525ea 100644 --- a/riscv/sv_insn_redirect.cc +++ b/riscv/sv_insn_redirect.cc @@ -587,11 +587,6 @@ OP_M64_FN( mulhu , sv_reg_t, sv_reg_t, sv_reg_t, uint64_t, uint64_t, uint64_t ) OP_M64_FN( mulhsu, sv_sreg_t, sv_reg_t, sv_sreg_t, int64_t, uint64_t, int64_t ) OP_M64_FN( mulh , sv_sreg_t, sv_sreg_t, sv_sreg_t, int64_t, int64_t, int64_t ) -sv_reg_t sv_proc_t::rv_sl(sv_reg_t const & lhs, sv_reg_t const & rhs) -{ - return rv_sl(lhs, rhs, xlen); -} - sv_reg_t sv_proc_t::rv_sl(sv_reg_t const & lhs, sv_reg_t const & rhs, unsigned int dflt_bitwidth) { @@ -608,11 +603,6 @@ sv_reg_t sv_proc_t::rv_sl(sv_reg_t const & lhs, sv_reg_t const & rhs, return rv_int_op_finish(lhs, rhs, result, bitwidth); } -sv_reg_t sv_proc_t::rv_sr(sv_reg_t const & lhs, sv_reg_t const & rhs) -{ - return rv_sr(lhs, rhs, xlen); -} - sv_reg_t sv_proc_t::rv_sr(sv_reg_t const & lhs, sv_reg_t const & rhs, unsigned int dflt_bitwidth) { diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h index ebac58f..c90eb67 100644 --- a/riscv/sv_insn_redirect.h +++ b/riscv/sv_insn_redirect.h @@ -136,10 +136,8 @@ public: sv_reg_t rv_and(sv_reg_t const & lhs, sv_reg_t const & rhs); sv_reg_t rv_or(sv_reg_t const & lhs, sv_reg_t const & rhs); sv_reg_t rv_xor(sv_reg_t const & lhs, sv_reg_t const & rhs); - sv_reg_t rv_sl(sv_reg_t const & lhs, sv_reg_t const & rhs); sv_reg_t rv_sl(sv_reg_t const & lhs, sv_reg_t const & rhs, unsigned int dflt_bitwidth); - sv_reg_t rv_sr(sv_reg_t const & lhs, sv_reg_t const & rhs); sv_reg_t rv_sr(sv_reg_t const & lhs, sv_reg_t const & rhs, unsigned int dflt_bitwidth); bool rv_lt(sv_reg_t const & lhs, sv_reg_t const & rhs); -- 2.30.2