From 001c9f1d45749535452d082a7c92a17954b603b8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 25 May 2018 15:41:45 +0200 Subject: [PATCH] Fix Verific handling of single-bit anyseq/anyconst wires Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 19273c69a..60fa6db3b 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -244,7 +244,9 @@ bool VerificImporter::import_netlist_instance_gates(Instance *inst, RTLIL::IdStr } if (inst->Type() == PRIM_BUF) { - module->addBufGate(inst_name, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput())); + auto outnet = inst->GetOutput(); + if (!any_all_nets.count(outnet)) + module->addBufGate(inst_name, net_map_at(inst->GetInput()), net_map_at(outnet)); return true; } @@ -1074,7 +1076,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se if (inst->Type() == PRIM_BUF) { auto outnet = inst->GetOutput(); - if (!anyconst_nets.count(outnet) && !anyseq_nets.count(outnet) && !allconst_nets.count(outnet) && !allseq_nets.count(outnet)) + if (!any_all_nets.count(outnet)) module->addBufGate(inst_name, net_map_at(inst->GetInput()), net_map_at(outnet)); continue; } -- 2.30.2