From 0022a940045b4dfc379556ed14df105362a3f5df Mon Sep 17 00:00:00 2001 From: David Mosberger-Tang Date: Sat, 4 Apr 1998 18:20:59 +0000 Subject: [PATCH] alpha.h (PRINT_OPERAND_PUNCT_VALID_P): Accept '(' for s/sv/svi. * alpha.h (PRINT_OPERAND_PUNCT_VALID_P): Accept '(' for s/sv/svi. * alpha.c (print_operand): Handle it. * alpha.md (fix_truncsfdi2): Use it. Add earlyclobber pattern for ALPHA_TP_INSN. (fix_truncdfdi2): Likewise. From-SVN: r18996 --- gcc/ChangeLog | 8 ++++++++ gcc/config/alpha/alpha.c | 19 +++++++++++++++++++ gcc/config/alpha/alpha.h | 8 ++++++-- gcc/config/alpha/alpha.md | 27 +++++++++++++++++++++++---- 4 files changed, 56 insertions(+), 6 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4cd6303c793..fc20ed2278f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +Sat Apr 4 18:07:16 1998 David Mosberger-Tang (davidm@mostang.com) + + * alpha.h (PRINT_OPERAND_PUNCT_VALID_P): Accept '(' for s/sv/svi. + * alpha.c (print_operand): Handle it. + * alpha.md (fix_truncsfdi2): Use it. Add earlyclobber pattern + for ALPHA_TP_INSN. + (fix_truncdfdi2): Likewise. + Sat Apr 4 17:42:05 1998 Richard Henderson * tree.h (sizetype_tab[2], sbitsizetype, ubitsizetype): Merge all diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c index 3888b984ccd..4c031e89bfa 100644 --- a/gcc/config/alpha/alpha.c +++ b/gcc/config/alpha/alpha.c @@ -2374,6 +2374,25 @@ print_operand (file, x, code) fputs ("su", file); break; + case '(': + /* Generates trap-mode suffix for instructions that accept the + v, sv, and svi suffix. The only instruction that needs this + is cvttq. */ + switch (alpha_fptm) + { + case ALPHA_FPTM_N: + case ALPHA_FPTM_U: + fputs ("v", file); + break; + case ALPHA_FPTM_SU: + fputs ("sv", file); + break; + case ALPHA_FPTM_SUI: + fputs ("svi", file); + break; + } + break; + case ')': /* Generates trap-mode suffix for instructions that accept the u, su, and sui suffix. This is the bulk of the IEEE floating point diff --git a/gcc/config/alpha/alpha.h b/gcc/config/alpha/alpha.h index da8f6968159..9c83d9975aa 100644 --- a/gcc/config/alpha/alpha.h +++ b/gcc/config/alpha/alpha.h @@ -2139,6 +2139,10 @@ do { \ ' Generates trap-mode suffix for instructions that accept the su suffix only (cmpt et al). + ( Generates trap-mode suffix for instructions that accept the + v, sv, and svi suffix. The only instruction that needs this + is cvttq. + ) Generates trap-mode suffix for instructions that accept the u, su, and sui suffix. This is the bulk of the IEEE floating point instructions (addt et al). @@ -2154,8 +2158,8 @@ do { \ */ #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ - ((CODE) == '&' || (CODE) == '\'' || (CODE) == ')' || (CODE) == '+' \ - || (CODE) == ',' || (CODE) == '-') + ((CODE) == '&' || (CODE) == '\'' || (CODE) == '(' || (CODE) == ')' \ + || (CODE) == '+' || (CODE) == ',' || (CODE) == '-') /* Print a memory address as an operand to reference that memory location. */ diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index 93f7e5f3bad..d54df8c8ee4 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -1771,20 +1771,39 @@ [(set_attr "type" "fadd") (set_attr "trap" "yes")]) +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=&f") + (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))] + "TARGET_FP && alpha_tp == ALPHA_TP_INSN" + "cvt%-q%(c %R1,%0" + [(set_attr "type" "fadd") + (set_attr "trap" "yes")]) + (define_insn "fix_truncdfdi2" [(set (match_operand:DI 0 "register_operand" "=f") (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))] "TARGET_FP" - "cvt%-qc %R1,%0" - [(set_attr "type" "fadd")]) + "cvt%-q%(c %R1,%0" + [(set_attr "type" "fadd") + (set_attr "trap" "yes")]) + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=&f") + (fix:DI (float_extend:DF + (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))] + "TARGET_FP && alpha_tp == ALPHA_TP_INSN" + "cvt%-q%(c %R1,%0" + [(set_attr "type" "fadd") + (set_attr "trap" "yes")]) (define_insn "fix_truncsfdi2" [(set (match_operand:DI 0 "register_operand" "=f") (fix:DI (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))] "TARGET_FP" - "cvt%-qc %R1,%0" - [(set_attr "type" "fadd")]) + "cvt%-q%(c %R1,%0" + [(set_attr "type" "fadd") + (set_attr "trap" "yes")]) (define_insn "" [(set (match_operand:SF 0 "register_operand" "=&f") -- 2.30.2