From 003f1950cdefd9decd3569ce3db6bf6caa9db68a Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 23 Mar 2013 19:37:16 +0100 Subject: [PATCH] xilinx_ise: fix clock domain names --- mibuild/xilinx_ise.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py index fe76b2ec..7d194c53 100644 --- a/mibuild/xilinx_ise.py +++ b/mibuild/xilinx_ise.py @@ -17,7 +17,7 @@ TIMESPEC "TSclk" = PERIOD "GRPclk" """+str(period)+""" ns HIGH 50%;""", clk=clk) class CRG_SE(SimpleCRG): def __init__(self, platform, clk_name, rst_name, period, rst_invert=False): SimpleCRG.__init__(self, platform, clk_name, rst_name, rst_invert) - _add_period_constraint(platform, self.cd.clk, period) + _add_period_constraint(platform, self.cd_sys.clk, period) class CRG_DS(Module): def __init__(self, platform, clk_name, rst_name, period, rst_invert=False): @@ -27,12 +27,12 @@ class CRG_DS(Module): rst_n = platform.request(rst_name) self.comb += self.cd_sys.rst.eq(~rst_n) else: - platform.request(rst_name, None, self.cd.rst) + platform.request(rst_name, None, self.cd_sys.rst) _add_period_constraint(platform, self._clk.p, period) self.specials += Instance("IBUFGDS", Instance.Input("I", self._clk.p), Instance.Input("IB", self._clk.n), - Instance.Output("O", self.cd.clk) + Instance.Output("O", self.cd_sys.clk) ) def _format_constraint(c): -- 2.30.2