From 005c4f04d415b23dafb341d1ce7293b64a3eeda5 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Tue, 16 Feb 2021 20:07:59 +0100 Subject: [PATCH] dcache error handling --- src/soc/fu/mmu/fsm.py | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py index c57c4a58..b1576e3f 100644 --- a/src/soc/fu/mmu/fsm.py +++ b/src/soc/fu/mmu/fsm.py @@ -38,6 +38,7 @@ class LoadStore1(PortInterfaceBase): #m.d.comb += self.l_in.valid.eq(1) #m.d.comb += self.d_in.load.eq(0) #m.d.comb += self.l_in.load.eq(0) + # set phys addr on both units m.d.comb += self.d_in.addr.eq(addr) m.d.comb += self.l_in.addr.eq(addr) # TODO set mask @@ -66,6 +67,26 @@ class LoadStore1(PortInterfaceBase): data = self.d_out.data return data, ld_ok + """ + if d_in.error = '1' then + if d_in.cache_paradox = '1' then + -- signal an interrupt straight away + exception := '1'; + dsisr(63 - 38) := not r2.req.load; + -- XXX there is no architected bit for this + -- (probably should be a machine check in fact) + dsisr(63 - 35) := d_in.cache_paradox; + else + -- Look up the translation for TLB miss + -- and also for permission error and RC error + -- in case the PTE has been updated. + mmureq := '1'; + v.state := MMU_LOOKUP; + v.stage1_en := '0'; + end if; + end if; + """ + def elaborate(self, platform): m = super().elaborate(platform) -- 2.30.2