From 0065b24b737bbd4d9ebac54001833c2348e51d71 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 5 Jul 2019 23:03:35 +0100 Subject: [PATCH] fix fcvt to work with new InputTest and pspec --- src/ieee754/fcvt/pipeline.py | 2 +- src/ieee754/fpcommon/test/fpmux.py | 10 +++++++--- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/src/ieee754/fcvt/pipeline.py b/src/ieee754/fcvt/pipeline.py index c5c9dea9..7926be9a 100644 --- a/src/ieee754/fcvt/pipeline.py +++ b/src/ieee754/fcvt/pipeline.py @@ -197,7 +197,7 @@ class FPCVTMuxInOut(ReservationStations): self.in_pspec = {} self.in_pspec['id_wid'] = self.id_wid self.in_pspec['op_wid'] = self.op_wid - self.in_pspec['width'] = self.in_width + self.in_pspec['width'] = in_width self.out_pspec = {} self.out_pspec['id_wid'] = self.out_id_wid diff --git a/src/ieee754/fpcommon/test/fpmux.py b/src/ieee754/fpcommon/test/fpmux.py index 5f066dfb..5cbdf23d 100644 --- a/src/ieee754/fpcommon/test/fpmux.py +++ b/src/ieee754/fpcommon/test/fpmux.py @@ -27,7 +27,7 @@ class InputTest: if self.single_op: (op1, ) = vals.pop(0) res = self.fpop(self.fpkls(op1)) - self.di[muxid][i] = (op1, op2) + self.di[muxid][i] = (op1, ) else: (op1, op2, ) = vals.pop(0) res = self.fpop(self.fpkls(op1), self.fpkls(op2)) @@ -36,11 +36,15 @@ class InputTest: def send(self, muxid): for i in range(self.tlen): - op1, op2 = self.di[muxid][i] + if self.single_op: + op1, = self.di[muxid][i] + else: + op1, op2 = self.di[muxid][i] rs = self.dut.p[muxid] yield rs.valid_i.eq(1) yield rs.data_i.a.eq(op1) - yield rs.data_i.b.eq(op2) + if not self.single_op: + yield rs.data_i.b.eq(op2) yield rs.data_i.muxid.eq(muxid) yield o_p_ready = yield rs.ready_o -- 2.30.2