From 006a05dbea6682535341b8d6be5627f2733d3ead Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 25 Sep 2021 20:20:24 +0100 Subject: [PATCH] comments --- src/soc/simple/test/test_runner.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py index e4e109ec..32c19db5 100644 --- a/src/soc/simple/test/test_runner.py +++ b/src/soc/simple/test/test_runner.py @@ -381,6 +381,8 @@ class TestRunner(FHDLTestCase): simrun = SimRunner(self, m, pspec) # run core clock at same rate as test clock + # XXX this has to stay here! TODO, work out why, + # but Simulation-only fails without it intclk = ClockSignal("coresync") comb += intclk.eq(ClockSignal()) -- 2.30.2