From 006b59a91b37cf4fba0fd0786a00462afe84a64e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 11 Sep 2022 20:46:58 +0100 Subject: [PATCH] mention aliases --- openpower/sv/rfc/ls001.mdwn | 1 + 1 file changed, 1 insertion(+) diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index 254a66010..b222975dd 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -136,6 +136,7 @@ such large numbers of registers, even for Multi-Issue microarchitectures. * To hold all Vector Context, five SPRs are needed for userspace. If Supervisor and Hypervisor mode are to also support Simple-V they will correspondingly need five SPRs each. + (Some 32/32-to-64 aliases are advantageous but not critical). * Five 6-bit XO (A-Form) "Management" instructions are needed. These are Scalar 32-bit instructions and *may* be 64-bit-extended in future (safely within the SVP64 space: no need for an EXT001 encoding). -- 2.30.2