From 008f95a043dac909f6e647c3102f37bb978b148c Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Thu, 23 Jan 2020 23:01:32 -0800 Subject: [PATCH] intel/fs: Add virtual instruction to load mask of live channels into flag register. Reviewed-by: Caio Marcelo de Oliveira Filho Cc: 20.0 --- src/intel/compiler/brw_eu_defines.h | 6 ++++++ src/intel/compiler/brw_fs.cpp | 3 ++- src/intel/compiler/brw_fs_cse.cpp | 1 + src/intel/compiler/brw_fs_generator.cpp | 11 ++++++++++- src/intel/compiler/brw_shader.cpp | 3 +++ 5 files changed, 22 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h index c83a478b908..779bab04235 100644 --- a/src/intel/compiler/brw_eu_defines.h +++ b/src/intel/compiler/brw_eu_defines.h @@ -490,6 +490,12 @@ enum opcode { */ SHADER_OPCODE_FIND_LIVE_CHANNEL, + /** + * Return the current execution mask in the specified flag subregister. + * Can be CSE'ed more easily than a plain MOV from the ce0 ARF register. + */ + FS_OPCODE_LOAD_LIVE_CHANNELS, + /** * Pick the channel from its first source register given by the index * specified as second source. Useful for variable indexing of surfaces. diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index d54fa7a640b..1b582cda0cd 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -1088,7 +1088,8 @@ fs_inst::flags_written() const opcode != BRW_OPCODE_WHILE)) || opcode == FS_OPCODE_FB_WRITE) { return flag_mask(this, 1); - } else if (opcode == SHADER_OPCODE_FIND_LIVE_CHANNEL) { + } else if (opcode == SHADER_OPCODE_FIND_LIVE_CHANNEL || + opcode == FS_OPCODE_LOAD_LIVE_CHANNELS) { return flag_mask(this, 32); } else { return flag_mask(dst, size_written); diff --git a/src/intel/compiler/brw_fs_cse.cpp b/src/intel/compiler/brw_fs_cse.cpp index 4751e11bcfe..f02914e04f3 100644 --- a/src/intel/compiler/brw_fs_cse.cpp +++ b/src/intel/compiler/brw_fs_cse.cpp @@ -76,6 +76,7 @@ is_expression(const fs_visitor *v, const fs_inst *const inst) case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL: case FS_OPCODE_LINTERP: case SHADER_OPCODE_FIND_LIVE_CHANNEL: + case FS_OPCODE_LOAD_LIVE_CHANNELS: case SHADER_OPCODE_BROADCAST: case SHADER_OPCODE_MOV_INDIRECT: case SHADER_OPCODE_TEX_LOGICAL: diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index 4f7bc159f07..00b0f29ef7b 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -2224,7 +2224,16 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, brw_find_live_channel(p, dst, mask); break; } - + case FS_OPCODE_LOAD_LIVE_CHANNELS: { + assert(devinfo->gen >= 8); + assert(inst->force_writemask_all && inst->group == 0); + assert(inst->dst.file == BAD_FILE); + brw_set_default_exec_size(p, BRW_EXECUTE_1); + brw_MOV(p, retype(brw_flag_subreg(inst->flag_subreg), + BRW_REGISTER_TYPE_UD), + retype(brw_mask_reg(0), BRW_REGISTER_TYPE_UD)); + break; + } case SHADER_OPCODE_BROADCAST: assert(inst->force_writemask_all); brw_broadcast(p, dst, src[0], src[1]); diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp index 1906c1fff1b..0a3c3739aa2 100644 --- a/src/intel/compiler/brw_shader.cpp +++ b/src/intel/compiler/brw_shader.cpp @@ -364,6 +364,9 @@ brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op) case SHADER_OPCODE_FIND_LIVE_CHANNEL: return "find_live_channel"; + case FS_OPCODE_LOAD_LIVE_CHANNELS: + return "load_live_channels"; + case SHADER_OPCODE_BROADCAST: return "broadcast"; case SHADER_OPCODE_SHUFFLE: -- 2.30.2