From 009cf8e01097581fa5a2f9306441ff8c0b03297e Mon Sep 17 00:00:00 2001 From: Doug Evans Date: Wed, 2 Mar 1994 00:41:51 +0000 Subject: [PATCH] (all floating point): If -msoft-float, don't allow any floating point builtin operations. From-SVN: r6689 --- gcc/config/a29k/a29k.md | 52 ++++++++++++++++++++--------------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/gcc/config/a29k/a29k.md b/gcc/config/a29k/a29k.md index 5290c0efcc9..11ea2102a8a 100644 --- a/gcc/config/a29k/a29k.md +++ b/gcc/config/a29k/a29k.md @@ -277,61 +277,61 @@ (define_insn "fix_truncsfsi2" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (fix:SI (match_operand:SF 1 "register_operand" "r")))] - "" + "! TARGET_SOFT_FLOAT" "convert %0,%1,0,3,0,1") (define_insn "fix_truncdfsi2" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (fix:SI (match_operand:DF 1 "register_operand" "r")))] - "" + "! TARGET_SOFT_FLOAT" "convert %0,%1,0,3,0,2") (define_insn "fixuns_truncsfsi2" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (unsigned_fix:SI (match_operand:SF 1 "register_operand" "r")))] - "" + "! TARGET_SOFT_FLOAT" "convert %0,%1,1,3,0,1") (define_insn "fixuns_truncdfsi2" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (unsigned_fix:SI (match_operand:DF 1 "register_operand" "r")))] - "" + "! TARGET_SOFT_FLOAT" "convert %0,%1,1,3,0,2") (define_insn "truncdfsf2" [(set (match_operand:SF 0 "register_operand" "=r") (float_truncate:SF (match_operand:DF 1 "register_operand" "r")))] - "" + "! TARGET_SOFT_FLOAT" "convert %0,%1,0,4,1,2") (define_insn "extendsfdf2" [(set (match_operand:DF 0 "register_operand" "=r") (float_extend:DF (match_operand:SF 1 "register_operand" "r")))] - "" + "! TARGET_SOFT_FLOAT" "convert %0,%1,0,4,2,1") (define_insn "floatsisf2" [(set (match_operand:SF 0 "register_operand" "=r") (float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))] - "" + "! TARGET_SOFT_FLOAT" "convert %0,%1,0,4,1,0") (define_insn "floatsidf2" [(set (match_operand:DF 0 "register_operand" "=r") (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))] - "" + "! TARGET_SOFT_FLOAT" "convert %0,%1,0,4,2,0") (define_insn "floatunssisf2" [(set (match_operand:SF 0 "register_operand" "=r") (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))] - "" + "! TARGET_SOFT_FLOAT" "convert %0,%1,1,4,1,0") (define_insn "floatunssidf2" [(set (match_operand:DF 0 "register_operand" "=r") (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))] - "" + "! TARGET_SOFT_FLOAT" "convert %0,%1,1,4,2,0") ;; CPxxx, DEQ, DGT, DGE, FEQ, FGT, FGE @@ -348,7 +348,7 @@ (match_operator 3 "fp_comparison_operator" [(match_operand:SF 1 "register_operand" "r") (match_operand:SF 2 "register_operand" "r")]))] - "" + "! TARGET_SOFT_FLOAT" "f%J3 %0,%1,%2" [(set_attr "type" "fadd")]) @@ -357,7 +357,7 @@ (match_operator 3 "fp_comparison_operator" [(match_operand:DF 1 "register_operand" "r") (match_operand:DF 2 "register_operand" "r")]))] - "" + "! TARGET_SOFT_FLOAT" "d%J3 %0,%1,%2" [(set_attr "type" "fadd")]) @@ -366,7 +366,7 @@ [(set (match_operand:DF 0 "register_operand" "") (plus:DF (match_operand:DF 1 "register_operand" "") (match_operand:DF 2 "register_operand" "")))] - "" + "! TARGET_SOFT_FLOAT" "") (define_insn "" @@ -392,7 +392,7 @@ [(set (match_operand:DF 0 "register_operand" "=r") (div:DF (match_operand:DF 1 "register_operand" "=r") (match_operand:DF 2 "register_operand" "r")))] - "" + "! TARGET_SOFT_FLOAT" "ddiv %0,%1,%2" [(set_attr "type" "ddiv")]) @@ -535,7 +535,7 @@ [(set (match_operand:DF 0 "register_operand" "") (mult:DF (match_operand:DF 1 "register_operand" "") (match_operand:DF 2 "register_operand" "")))] - "" + "! TARGET_SOFT_FLOAT" "") (define_insn "" @@ -561,7 +561,7 @@ [(set (match_operand:DF 0 "register_operand" "=r") (minus:DF (match_operand:DF 1 "register_operand" "r") (match_operand:DF 2 "register_operand" "r")))] - "" + "! TARGET_SOFT_FLOAT" "") (define_insn "" @@ -731,7 +731,7 @@ [(set (match_operand:SF 0 "register_operand" "") (plus:SF (match_operand:SF 1 "register_operand" "") (match_operand:SF 2 "register_operand" "")))] - "" + "! TARGET_SOFT_FLOAT" "") (define_insn "" @@ -757,7 +757,7 @@ [(set (match_operand:SF 0 "register_operand" "=r") (div:SF (match_operand:SF 1 "register_operand" "=r") (match_operand:SF 2 "register_operand" "r")))] - "" + "! TARGET_SOFT_FLOAT" "fdiv %0,%1,%2" [(set_attr "type" "fdiv")]) @@ -766,7 +766,7 @@ [(set (match_operand:DF 0 "register_operand" "=r") (mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "%r")) (float_extend:DF (match_operand:SF 2 "register_operand" "r"))))] - "" + "! TARGET_SOFT_FLOAT" "fdmul %0,%1,%2") ;; FMAC/FMSM @@ -847,7 +847,7 @@ [(set (match_operand:SF 0 "register_operand" "") (mult:SF (match_operand:SF 1 "register_operand" "") (match_operand:SF 2 "register_operand" "")))] - "" + "! TARGET_SOFT_FLOAT" "") (define_insn "" @@ -873,7 +873,7 @@ [(set (match_operand:SF 0 "register_operand" "") (minus:SF (match_operand:SF 1 "register_operand" "") (match_operand:SF 2 "register_operand" "")))] - "" + "! TARGET_SOFT_FLOAT" "") (define_insn "" @@ -1531,7 +1531,7 @@ [(parallel [(set (match_operand:SF 0 "register_operand" "") (neg:SF (match_operand:SF 1 "register_operand" ""))) (clobber (match_scratch:SI 2 ""))])] - "" + "! TARGET_SOFT_FLOAT" " { rtx result; @@ -1559,7 +1559,7 @@ [(parallel [(set (match_operand:DF 0 "register_operand" "") (neg:DF (match_operand:DF 1 "register_operand" ""))) (clobber (match_scratch:SI 2 ""))])] - "" + "! TARGET_SOFT_FLOAT" " { rtx result; @@ -2430,7 +2430,7 @@ [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "") (match_operand:SF 1 "gpc_reg_operand" "")))] - "" + "! TARGET_SOFT_FLOAT" " { a29k_compare_op0 = operands[0]; @@ -2443,7 +2443,7 @@ [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "") (match_operand:DF 1 "gpc_reg_operand" "")))] - "" + "! TARGET_SOFT_FLOAT" " { a29k_compare_op0 = operands[0]; @@ -2663,7 +2663,7 @@ (match_operand 2 "gpc_reg_operand" ""))) (set (match_operand:SI 0 "gpc_reg_operand" "") (ge:SI (match_dup 3) (const_int 0)))] - "" + "! TARGET_SOFT_FLOAT" " { operands[3] = gen_reg_rtx (SImode); }"); -- 2.30.2