From 00a7f22152c2512020f2ad45d6c6b02ed230817d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 8 Jun 2019 14:30:25 +0100 Subject: [PATCH] convert FU_RW_Pend accumulator to src-vector --- src/scoreboard/fu_reg_matrix.py | 17 +++++++++-------- src/scoreboard/fu_wr_pending.py | 22 ++++++++++++---------- 2 files changed, 21 insertions(+), 18 deletions(-) diff --git a/src/scoreboard/fu_reg_matrix.py b/src/scoreboard/fu_reg_matrix.py index e8c7ceac..84aaeb89 100644 --- a/src/scoreboard/fu_reg_matrix.py +++ b/src/scoreboard/fu_reg_matrix.py @@ -37,12 +37,12 @@ class FURegDepMatrix(Elaboratable): src = [] rsel = [] for i in range(n_src): - j = i + 1 # name numbering to match src1/src2 + j = i + 1 # name numbering to match src1/src2 src.append(Signal(n_reg, name="src%d" % j, reset_less=True)) rsel.append(Signal(n_reg, name="src%d_rsel_o" % j, reset_less=True)) pend = [] for i in range(nf): - j = i + 1 # name numbering to match src1/src2 + j = i + 1 # name numbering to match src1/src2 pend.append(Signal(nf, name="rd_src%d_pend_o" % j, reset_less=True)) self.dest_i = Signal(n_reg_col, reset_less=True) # Dest in (top) @@ -74,7 +74,7 @@ class FURegDepMatrix(Elaboratable): # --- # matrix of dependency cells # --- - dm = Array(DependencyRow(self.n_reg_col, 2) \ + dm = Array(DependencyRow(self.n_reg_col, self.n_src) \ for r in range(self.n_fu_row)) for fu in range(self.n_fu_row): setattr(m.submodules, "dr_fu%d" % fu, dm[fu]) @@ -82,7 +82,8 @@ class FURegDepMatrix(Elaboratable): # --- # array of Function Unit Pending vectors # --- - fupend = Array(FU_RW_Pend(self.n_reg_col) for f in range(self.n_fu_row)) + fupend = Array(FU_RW_Pend(self.n_reg_col, self.n_src) \ + for f in range(self.n_fu_row)) for fu in range(self.n_fu_row): setattr(m.submodules, "fu_fu%d" % (fu), fupend[fu]) @@ -113,14 +114,14 @@ class FURegDepMatrix(Elaboratable): src2_fwd_o.append(dc.src_fwd_o[1][rn]) # connect cell fwd outputs to FU Vector in [Cat is gooood] m.d.comb += [fup.dest_fwd_i.eq(Cat(*dest_fwd_o)), - fup.src1_fwd_i.eq(Cat(*src1_fwd_o)), - fup.src2_fwd_i.eq(Cat(*src2_fwd_o)) + fup.src_fwd_i[0].eq(Cat(*src1_fwd_o)), + fup.src_fwd_i[1].eq(Cat(*src2_fwd_o)) ] # accumulate FU Vector outputs wr_pend.append(fup.reg_wr_pend_o) rd_pend.append(fup.reg_rd_pend_o) - rd_src1_pend.append(fup.reg_rd_src1_pend_o) - rd_src2_pend.append(fup.reg_rd_src2_pend_o) + rd_src1_pend.append(fup.reg_rd_src_pend_o[0]) + rd_src2_pend.append(fup.reg_rd_src_pend_o[1]) # ... and output them from this module (vertical, width=FUs) m.d.comb += self.wr_pend_o.eq(Cat(*wr_pend)) diff --git a/src/scoreboard/fu_wr_pending.py b/src/scoreboard/fu_wr_pending.py index abfca25f..d0bcb954 100644 --- a/src/scoreboard/fu_wr_pending.py +++ b/src/scoreboard/fu_wr_pending.py @@ -1,27 +1,29 @@ -from nmigen import Elaboratable, Module, Signal, Cat +from nmigen import Elaboratable, Module, Signal, Array class FU_RW_Pend(Elaboratable): """ these are allocated per-FU (horizontally), and are of length reg_count """ - def __init__(self, reg_count): + def __init__(self, reg_count, n_src): + self.n_src = n_src self.reg_count = reg_count self.dest_fwd_i = Signal(reg_count, reset_less=True) - self.src1_fwd_i = Signal(reg_count, reset_less=True) - self.src2_fwd_i = Signal(reg_count, reset_less=True) + src = [] + for i in range(n_src): + j = i + 1 # name numbering to match src1/src2 + src.append(Signal(reg_count, name="src%d" % j, reset_less=True)) + self.src_fwd_i = Array(src) self.reg_wr_pend_o = Signal(reset_less=True) self.reg_rd_pend_o = Signal(reset_less=True) - self.reg_rd_src1_pend_o = Signal(reset_less=True) - self.reg_rd_src2_pend_o = Signal(reset_less=True) + self.reg_rd_src_pend_o = Signal(n_src, reset_less=True) def elaborate(self, platform): m = Module() m.d.comb += self.reg_wr_pend_o.eq(self.dest_fwd_i.bool()) - m.d.comb += self.reg_rd_src1_pend_o.eq(self.src1_fwd_i.bool()) - m.d.comb += self.reg_rd_src2_pend_o.eq(self.src2_fwd_i.bool()) - m.d.comb += self.reg_rd_pend_o.eq(self.reg_rd_src1_pend_o | - self.reg_rd_src2_pend_o) + for i in range(self.n_src): + m.d.comb += self.reg_rd_src_pend_o[i].eq(self.src_fwd_i[i].bool()) + m.d.comb += self.reg_rd_pend_o.eq(self.reg_rd_src_pend_o.bool()) return m -- 2.30.2