From 00b85f43edd50da278e49a75ee921a606421d2d4 Mon Sep 17 00:00:00 2001 From: lkcl Date: Mon, 21 Dec 2020 05:02:00 +0000 Subject: [PATCH] --- openpower/sv/svp_rewrite/svp64.mdwn | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index f7af5b19a..924231da7 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -209,7 +209,6 @@ These are the modes: * **ffirst** or data-dependent fail-on-first: see separate section. the vector may be truncated depending on certain criteria. *VL is altered as a result*. * **sat mode** or saturation: clamps each elemrnt result to a min/max rather than overflows / wraps. allows signed and unsigned clamping. - requires twin-predication (different src and dest elwidth). * **reduce mode**. a mapreduce is performed. the result is a scalar. a result vector however is required, as the upper elements may be used to store intermediary computations. the result of the mapreduce is in the first element with a nonzero predicate bit. see separate section below. note that there are comprehensive caveats when using this mode. * **pred-result** will test the result (CR testing selects a bit of CR and inverts it, just like branch testing) and if the test fails it is as if the predicate bit was zero. When Rc=1 the CR element (CR0) however is still stored in the CR regfile. This scheme does not apply to crops (crand, cror). @@ -523,8 +522,7 @@ saturation may be done using a mapreduced CR op (cror), or by using the new crweird instruction, transferring the relevant CR bits to a scalar integer and testing it for nonzero. see [[sv/cr_int_predication]] -Note that due to the need for both a src and dest elwidth, saturation mode -requires twin-predication. +Note that the operation takes place at the maximum bitwidth (max of src and dest elwidth) and that truncation occurs to the range of the dest elwidth. ## Reduce mode -- 2.30.2