From 00ba656d95feaa71365ebc9bb6c8088f9a297ded Mon Sep 17 00:00:00 2001 From: Cesar Strauss Date: Sat, 6 Mar 2021 19:38:00 -0300 Subject: [PATCH] Allow updating the PC and SVSTATE registers while stopped While the fetch address was overridden by a PC reset, the PC register itself was updated (with NIA) only after the first instruction ended. Use the time while the core is stopped to recognise and update the PC and SVSTATE registers, before the first instruction starts. --- src/soc/simple/issuer.py | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index 6ba8b39d..f16eb8b5 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -276,6 +276,15 @@ class TestIssuerInternal(Elaboratable): with m.Else(): comb += core.core_stopped_i.eq(1) comb += dbg.core_stopped_i.eq(1) + # while stopped, allow updating the PC and SVSTATE + with m.If(self.pc_i.ok): + comb += self.state_w_pc.wen.eq(1 << StateRegs.PC) + comb += self.state_w_pc.data_i.eq(self.pc_i.data) + sync += pc_changed.eq(1) + with m.If(self.svstate_i.ok): + comb += new_svstate.eq(self.svstate_i.data) + comb += update_svstate.eq(1) + sync += sv_changed.eq(1) # go fetch the instruction at the current PC # at this point, there is no instruction running, that @@ -350,6 +359,15 @@ class TestIssuerInternal(Elaboratable): with m.Else(): comb += core.core_stopped_i.eq(1) comb += dbg.core_stopped_i.eq(1) + # while stopped, allow updating the PC and SVSTATE + with m.If(self.pc_i.ok): + comb += self.state_w_pc.wen.eq(1 << StateRegs.PC) + comb += self.state_w_pc.data_i.eq(self.pc_i.data) + sync += pc_changed.eq(1) + with m.If(self.svstate_i.ok): + comb += new_svstate.eq(self.svstate_i.data) + comb += update_svstate.eq(1) + sync += sv_changed.eq(1) # need to decode the instruction again, after updating SRCSTEP # in the previous state. -- 2.30.2