From 00bfdac5b8e20463c04b9ec3f67bf1392fb86205 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 26 Oct 2010 14:36:18 -0700 Subject: [PATCH] i965: Fix VS URB entry sizing. I'm trying to clamp to a minimum of 1 URB row, not a maximum of 1. Fixes: glsl-kwin-blur glsl-max-varying glsl-routing --- src/mesa/drivers/dri/i965/gen6_urb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/gen6_urb.c b/src/mesa/drivers/dri/i965/gen6_urb.c index 0a264fcd90e..a34123478fb 100644 --- a/src/mesa/drivers/dri/i965/gen6_urb.c +++ b/src/mesa/drivers/dri/i965/gen6_urb.c @@ -40,7 +40,7 @@ prepare_urb( struct brw_context *brw ) else brw->urb.nr_gs_entries = 0; /* CACHE_NEW_VS_PROG */ - brw->urb.vs_size = MIN2(brw->vs.prog_data->urb_entry_size, 1); + brw->urb.vs_size = MAX2(brw->vs.prog_data->urb_entry_size, 1); /* Check that the number of URB rows (8 floats each) allocated is less * than the URB space. -- 2.30.2