From 00c1351ec3698368a2507fa94f299828f0c0ed0c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 3 Jun 2021 13:02:34 +0100 Subject: [PATCH] whoops, in1_isvec and dec_bi are optional --- src/openpower/decoder/power_decoder2.py | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py index c9221481..b620d932 100644 --- a/src/openpower/decoder/power_decoder2.py +++ b/src/openpower/decoder/power_decoder2.py @@ -934,9 +934,9 @@ class PowerDecodeSubset(Elaboratable): comb += rm_dec.ptype_in.eq(op.SV_Ptype) # Single/Twin predicated comb += rm_dec.rc_in.eq(rc_out) # Rc=1 comb += rm_dec.rm_in.eq(self.sv_rm) # SVP64 RM mode - bzero = dec_bi.imm_out.ok & ~dec_bi.imm_out.data.bool() - comb += rm_dec.ldst_imz_in.eq(bzero) # B immediate is zero - comb += rm_dec.ldst_ra_vec.eq(self.in1_isvec) # RA is vector + if self.needs_field("imm_data", "in2_sel"): + bzero = dec_bi.imm_out.ok & ~dec_bi.imm_out.data.bool() + comb += rm_dec.ldst_imz_in.eq(bzero) # B immediate is zero # decoded/selected instruction flags comb += self.do_copy("data_len", self.op_get("ldst_len")) @@ -1261,6 +1261,9 @@ class PowerDecode2(PowerDecodeSubset): comb += to_reg.data.eq(fromreg.data) comb += to_reg.ok.eq(fromreg.ok) + if self.svp64_en: + comb += self.rm_dec.ldst_ra_vec.eq(self.in1_isvec) # RA is vector + # SPRs out comb += e.read_spr1.eq(dec_a.spr_out) comb += e.write_spr.eq(dec_o.spr_out) -- 2.30.2