From 00e8ef8d253c021ba39d3c21652467e386a46b54 Mon Sep 17 00:00:00 2001 From: Shriya Sharma Date: Tue, 19 Sep 2023 16:37:20 +0100 Subject: [PATCH] Added english description for lbzux instruction --- openpower/isa/fixedload.mdwn | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn index e66c461f..71059cb0 100644 --- a/openpower/isa/fixedload.mdwn +++ b/openpower/isa/fixedload.mdwn @@ -92,6 +92,12 @@ Pseudo-code: RT <- ([0] * (XLEN-8)) || MEM(EA, 1) RA <- EA +Description:Let the effective address (EA) be the sum (RA)+ (RB). +The byte in storage addressed by EA is loaded into +RT56:63. RT0:55 are set to 0. +EA is placed into register RA. +If RA=0 or RA=RT, the instruction form is invalid. + Special Registers Altered: None -- 2.30.2