From 01028af5e55f6eb81458d3ab58b95cabb78ad49d Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 10 Sep 2022 01:48:34 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls001.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index ba839a081..221b2881d 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -73,7 +73,7 @@ Illegal Instruction trap-and-emulate is also out of the question. **Simple-V guarantees binary interoperability** by defining fixed register file bitwidths and size for all instructions. This does -mean that **reserved** space is important to have in SVP64, in order +mean that `RESERVED` space is important to have in SVP64, in order to provide future expanded register file bitwidths and sizes. # Hardware Implementations -- 2.30.2