From 013606868736fad0d1f475ff3c113c4e20548568 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 13 Feb 2022 14:03:30 +0000 Subject: [PATCH] start adding uart16550 --- examples/soc.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/examples/soc.py b/examples/soc.py index 2389e07..54ffdd3 100644 --- a/examples/soc.py +++ b/examples/soc.py @@ -7,6 +7,7 @@ # Modifications for the Libre-SOC Project funded by NLnet and NGI POINTER # under EU Grants 871528 and 957073, under the LGPLv3+ License +from soc.bus.uart_16550 import UART16550 # opencores 16550 uart from nmigen import (Module, Elaboratable, DomainRenamer) from nmigen.lib.cdc import ResetSynchronizer from nmigen_soc import wishbone, memory @@ -14,7 +15,6 @@ from nmigen_stdio.serial import AsyncSerial from lambdasoc.cpu.minerva import MinervaCPU from lambdasoc.periph.intc import GenericInterruptController -from lambdasoc.periph.serial import AsyncSerialPeripheral from lambdasoc.periph.sram import SRAMPeripheral from lambdasoc.periph.timer import TimerPeripheral from lambdasoc.periph import Peripheral @@ -30,10 +30,10 @@ from nmigen_boards.ulx3s import ULX3S_85F_Platform from nmigen_boards.arty_a7 import ArtyA7_100Platform from nmigen_boards.test.blinky import Blinky -from uartbridge import UARTBridge from crg import ECPIX5CRG import sys +import os class DDR3SoC(SoC, Elaboratable): @@ -81,10 +81,10 @@ class DDR3SoC(SoC, Elaboratable): self._decoder.add(self.ram.bus, addr=0x8000000) # SRAM at 0x8000_000 # UART - self.uart_phy = AsyncSerial(data_bits=8, - divisor=int(clk_freq//115200), - pins=uart_pins) - self.uart = AsyncSerialPeripheral(core=self.uart_phy) + opencores_16550 = "../../uart16550/rtl/verilog" + pth = __file__ + print (pth) + self.uart = UART16550(verilog_src_dir=opencores_16550) self._decoder.add(self.uart.bus, addr=0xc0002000) # 16550 UART address # DRAM Module -- 2.30.2