From 0168f83523b927bc81576fc2b16a91062310112c Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 15 Mar 2013 19:51:29 +0100 Subject: [PATCH] MultiReg: remove idomain --- milkymist/dvisampler/edid.py | 4 ++-- milkymist/uart/__init__.py | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/milkymist/dvisampler/edid.py b/milkymist/dvisampler/edid.py index 48fb69e2..89c29799 100644 --- a/milkymist/dvisampler/edid.py +++ b/milkymist/dvisampler/edid.py @@ -33,9 +33,9 @@ class EDID(Module, AutoReg): _sda_i_async = Signal() self.sync += _sda_drv_reg.eq(sda_drv) self.specials += [ - MultiReg(self.scl, "ext", scl_i, "sys"), + MultiReg(self.scl, scl_i, "sys"), Tristate(self.sda, 0, _sda_drv_reg, _sda_i_async), - MultiReg(_sda_i_async, "ext", sda_i, "sys") + MultiReg(_sda_i_async, sda_i, "sys") ] # FIXME: understand what is really going on here and get rid of that workaround diff --git a/milkymist/uart/__init__.py b/milkymist/uart/__init__.py index 8dd903f0..8a129746 100644 --- a/milkymist/uart/__init__.py +++ b/milkymist/uart/__init__.py @@ -59,7 +59,7 @@ class UART(Module, AutoReg): # RX rx = Signal() - self.specials += MultiReg(self.rx, "ext", rx, "sys") + self.specials += MultiReg(self.rx, rx, "sys") rx_r = Signal() rx_reg = Signal(8) rx_bitcount = Signal(4) -- 2.30.2