From 01737f42d8416c7b155cb84e25d53f73530ad3a3 Mon Sep 17 00:00:00 2001 From: Andrew Cagney Date: Sun, 1 Feb 1998 03:29:48 +0000 Subject: [PATCH] mips: Add multi-processor support for r5900. Others might work. common, igen: Fix MP related bugs. --- sim/common/ChangeLog | 5 + sim/mips/ChangeLog | 46 +++++ sim/mips/configure | 125 +++++++----- sim/mips/configure.in | 16 +- sim/mips/interp.c | 429 +++++++++++++++++++++++------------------- sim/mips/mdmx.igen | 29 ++- sim/mips/sim-main.h | 139 +++++++------- 7 files changed, 465 insertions(+), 324 deletions(-) diff --git a/sim/common/ChangeLog b/sim/common/ChangeLog index 67bee19d488..4d9e270629b 100644 --- a/sim/common/ChangeLog +++ b/sim/common/ChangeLog @@ -1,3 +1,8 @@ +Sun Feb 1 14:02:31 1998 Andrew Cagney + + * sim-profile.c (profile_print): Only print CPU if other + output is going to appear. + Sat Jan 31 18:15:41 1998 Andrew Cagney * configure: Regenerated to track ../common/aclocal.m4 changes. diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index 05d8d101fbc..c7205d6b77c 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,3 +1,49 @@ +Sun Feb 1 11:15:29 1998 Andrew Cagney + + * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in + size. + + * interp.c (SD, CPU): Define. + (mips_option_handler): Set flags in each CPU. + (interrupt_event): Assume CPU 0 is the one being iterrupted. + (sim_close): Do not clear STATE, deleted anyway. + (sim_write, sim_read): Assume CPU zero's vm should be used for + data transfers. + (sim_create_inferior): Set the PC for all processors. + (sim_monitor, store_word, load_word, mips16_entry): Add cpu + argument. + (mips16_entry): Pass correct nr of args to store_word, load_word. + (ColdReset): Cold reset all cpu's. + (signal_exception): Pass cpu to sim_monitor & mips16_entry. + (sim_monitor, load_memory, store_memory, signal_exception): Use + `CPU' instead of STATE_CPU. + + + * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with + SD or CPU_. + + * sim-main.h (signal_exception): Add sim_cpu arg. + (SignalException*): Pass both SD and CPU to signal_exception. + * interp.c (signal_exception): Update. + + * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c: + Ditto + (sync_operation, prefetch, cache_op, store_memory, load_memory, + address_translation): Ditto + (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto. + +start-sanitize-vr5400 + * mdmx.igen (get_scale): Pass CPU_ to semantic_illegal instead of + `sd'. + (ByteAlign): Use StoreFPR, pass args in correct order. + +end-sanitize-vr5400 +start-sanitize-r5900 +Sun Feb 1 10:59:55 1998 Andrew Cagney + + * configure.in (sim_igen_filter): For r5900, configure as SMP. + +end-sanitize-r5900 Sat Jan 31 18:15:41 1998 Andrew Cagney * configure: Regenerated to track ../common/aclocal.m4 changes. diff --git a/sim/mips/configure b/sim/mips/configure index a150a538850..0eca7428eb9 100755 --- a/sim/mips/configure +++ b/sim/mips/configure @@ -114,6 +114,8 @@ ac_help="$ac_help --enable-sim-bitsize=N Specify target bitsize (32 or 64)." ac_help="$ac_help --enable-sim-float Specify that the target processor has floating point hardware." +ac_help="$ac_help + --enable-sim-smp=n Specify number of processors to configure for (default ${default_sim_smp})." ac_help="$ac_help --enable-sim-igen=opts Enable IGEN simulator" @@ -625,7 +627,7 @@ fi echo $ac_n "checking how to run the C preprocessor""... $ac_c" 1>&6 -echo "configure:629: checking how to run the C preprocessor" >&5 +echo "configure:631: checking how to run the C preprocessor" >&5 # On Suns, sometimes $CPP names a directory. if test -n "$CPP" && test -d "$CPP"; then CPP= @@ -640,13 +642,13 @@ else # On the NeXT, cc -E runs the code through the compiler's parser, # not just through cpp. cat > conftest.$ac_ext < Syntax Error EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:650: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:652: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out` if test -z "$ac_err"; then : @@ -657,13 +659,13 @@ else rm -rf conftest* CPP="${CC-cc} -E -traditional-cpp" cat > conftest.$ac_ext < Syntax Error EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:667: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:669: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out` if test -z "$ac_err"; then : @@ -736,7 +738,7 @@ else { echo "configure: error: can not run $ac_config_sub" 1>&2; exit 1; } fi echo $ac_n "checking host system type""... $ac_c" 1>&6 -echo "configure:740: checking host system type" >&5 +echo "configure:742: checking host system type" >&5 host_alias=$host case "$host_alias" in @@ -757,7 +759,7 @@ host_os=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` echo "$ac_t""$host" 1>&6 echo $ac_n "checking target system type""... $ac_c" 1>&6 -echo "configure:761: checking target system type" >&5 +echo "configure:763: checking target system type" >&5 target_alias=$target case "$target_alias" in @@ -775,7 +777,7 @@ target_os=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` echo "$ac_t""$target" 1>&6 echo $ac_n "checking build system type""... $ac_c" 1>&6 -echo "configure:779: checking build system type" >&5 +echo "configure:781: checking build system type" >&5 build_alias=$build case "$build_alias" in @@ -819,7 +821,7 @@ test "$program_transform_name" = "" && program_transform_name="s,x,x," # Extract the first word of "gcc", so it can be a program name with args. set dummy gcc; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:823: checking for $ac_word" >&5 +echo "configure:825: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -848,7 +850,7 @@ if test -z "$CC"; then # Extract the first word of "cc", so it can be a program name with args. set dummy cc; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:852: checking for $ac_word" >&5 +echo "configure:854: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -896,7 +898,7 @@ fi fi echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6 -echo "configure:900: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5 +echo "configure:902: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5 ac_ext=c # CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. @@ -906,11 +908,11 @@ ac_link='${CC-cc} -o conftest $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS cross_compiling=$ac_cv_prog_cc_cross cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest; then +if { (eval echo configure:916: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then ac_cv_prog_cc_works=yes # If we can't run a trivial program, we are probably using a cross compiler. if (./conftest; exit) 2>/dev/null; then @@ -930,12 +932,12 @@ if test $ac_cv_prog_cc_works = no; then { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; } fi echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6 -echo "configure:934: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5 +echo "configure:936: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5 echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6 cross_compiling=$ac_cv_prog_cc_cross echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6 -echo "configure:939: checking whether we are using GNU C" >&5 +echo "configure:941: checking whether we are using GNU C" >&5 if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -944,7 +946,7 @@ else yes; #endif EOF -if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:948: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then +if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:950: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then ac_cv_prog_gcc=yes else ac_cv_prog_gcc=no @@ -959,7 +961,7 @@ if test $ac_cv_prog_gcc = yes; then ac_save_CFLAGS="$CFLAGS" CFLAGS= echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6 -echo "configure:963: checking whether ${CC-cc} accepts -g" >&5 +echo "configure:965: checking whether ${CC-cc} accepts -g" >&5 if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -997,7 +999,7 @@ fi # SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff" # ./install, which can be erroneously created by make from ./install.sh. echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6 -echo "configure:1001: checking for a BSD compatible install" >&5 +echo "configure:1003: checking for a BSD compatible install" >&5 if test -z "$INSTALL"; then if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -1062,7 +1064,7 @@ AR=${AR-ar} # Extract the first word of "ranlib", so it can be a program name with args. set dummy ranlib; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:1066: checking for $ac_word" >&5 +echo "configure:1068: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1096,17 +1098,17 @@ for ac_hdr in stdlib.h string.h strings.h unistd.h time.h sys/time.h sys/resourc do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:1100: checking for $ac_hdr" >&5 +echo "configure:1102: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext < EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:1110: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:1112: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out` if test -z "$ac_err"; then rm -rf conftest* @@ -1135,12 +1137,12 @@ done for ac_func in getrusage time sigaction do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:1139: checking for $ac_func" >&5 +echo "configure:1141: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest; then +if { (eval echo configure:1169: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -1335,12 +1337,12 @@ fi echo $ac_n "checking return type of signal handlers""... $ac_c" 1>&6 -echo "configure:1339: checking return type of signal handlers" >&5 +echo "configure:1341: checking return type of signal handlers" >&5 if eval "test \"`echo '$''{'ac_cv_type_signal'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext < #include @@ -1357,7 +1359,7 @@ int main() { int i; ; return 0; } EOF -if { (eval echo configure:1361: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:1363: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* ac_cv_type_signal=void else @@ -1501,14 +1503,14 @@ else if test "x$cross_compiling" = "xno"; then echo $ac_n "checking whether byte ordering is bigendian""... $ac_c" 1>&6 -echo "configure:1505: checking whether byte ordering is bigendian" >&5 +echo "configure:1507: checking whether byte ordering is bigendian" >&5 if eval "test \"`echo '$''{'ac_cv_c_bigendian'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else ac_cv_c_bigendian=unknown # See if sys/param.h defines the BYTE_ORDER macro. cat > conftest.$ac_ext < #include @@ -1519,11 +1521,11 @@ int main() { #endif ; return 0; } EOF -if { (eval echo configure:1523: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:1525: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* # It does; now see whether it defined to BIG_ENDIAN or not. cat > conftest.$ac_ext < #include @@ -1534,7 +1536,7 @@ int main() { #endif ; return 0; } EOF -if { (eval echo configure:1538: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:1540: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* ac_cv_c_bigendian=yes else @@ -1554,7 +1556,7 @@ if test "$cross_compiling" = yes; then { echo "configure: error: can not run test program while cross compiling" 1>&2; exit 1; } else cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest && (./conftest; exit) 2>/dev/null +if { (eval echo configure:1573: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest && (./conftest; exit) 2>/dev/null then ac_cv_c_bigendian=no else @@ -1822,6 +1824,37 @@ fi +# +# Select the level of SMP support +# +case "${target}" in +# start-sanitize-r5900 + mips64r59*-*-*) mips_smp=1 ;; +# end-sanitize-r5900 + *) mips_smp=0 ;; +esac + +default_sim_smp="$mips_smp" +# Check whether --enable-sim-smp or --disable-sim-smp was given. +if test "${enable_sim_smp+set}" = set; then + enableval="$enable_sim_smp" + case "${enableval}" in + yes) sim_smp="-DWITH_SMP=5" ; sim_igen_smp="-N 5";; + no) sim_smp="-DWITH_SMP=0" ; sim_igen_smp="-N 0";; + *) sim_smp="-DWITH_SMP=$enableval" ; sim_igen_smp="-N $enableval";; +esac +if test x"$silent" != x"yes" && test x"$sim_smp" != x""; then + echo "Setting smp flags = $sim_smp" 6>&1 +fi +else + sim_smp="-DWITH_SMP=${default_sim_smp}" ; sim_igen_smp="-N ${default_sim_smp}" +if test x"$silent" != x"yes"; then + echo "Setting smp flags = $sim_smp" 6>&1 +fi +fi + + + # # Select the IGEN architecture # @@ -1867,8 +1900,8 @@ case "${target}" in *) sim_default_gen=IGEN ;; esac -sim_igen_flags="-F ${sim_igen_filter} ${sim_igen_machine}" -sim_m16_flags=" -F ${sim_m16_filter} ${sim_m16_machine}" +sim_igen_flags="-F ${sim_igen_filter} ${sim_igen_machine} ${sim_igen_smp}" +sim_m16_flags=" -F ${sim_m16_filter} ${sim_m16_machine} ${sim_igen_smp}" @@ -1898,17 +1931,17 @@ for ac_hdr in string.h strings.h stdlib.h stdlib.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:1902: checking for $ac_hdr" >&5 +echo "configure:1935: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext < EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:1912: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:1945: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out` if test -z "$ac_err"; then rm -rf conftest* @@ -1935,7 +1968,7 @@ fi done echo $ac_n "checking for fabs in -lm""... $ac_c" 1>&6 -echo "configure:1939: checking for fabs in -lm" >&5 +echo "configure:1972: checking for fabs in -lm" >&5 ac_lib_var=`echo m'_'fabs | sed 'y%./+-%__p_%'` if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -1943,7 +1976,7 @@ else ac_save_LIBS="$LIBS" LIBS="-lm $LIBS" cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest; then +if { (eval echo configure:1991: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then rm -rf conftest* eval "ac_cv_lib_$ac_lib_var=yes" else @@ -1984,12 +2017,12 @@ fi for ac_func in aint anint sqrt do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:1988: checking for $ac_func" >&5 +echo "configure:2021: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <&5; (eval $ac_link) 2>&5; } && test -s conftest; then +if { (eval echo configure:2049: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else diff --git a/sim/mips/configure.in b/sim/mips/configure.in index 710dbe72011..9ebf0b40fd2 100644 --- a/sim/mips/configure.in +++ b/sim/mips/configure.in @@ -96,6 +96,18 @@ esac SIM_AC_OPTION_FLOAT($mips_fpu) +# +# Select the level of SMP support +# +case "${target}" in +# start-sanitize-r5900 + mips64r59*-*-*) mips_smp=1 ;; +# end-sanitize-r5900 + *) mips_smp=0 ;; +esac +SIM_AC_OPTION_SMP($mips_smp) + + # # Select the IGEN architecture # @@ -141,8 +153,8 @@ case "${target}" in *) sim_default_gen=IGEN ;; esac -sim_igen_flags="-F ${sim_igen_filter} ${sim_igen_machine}" -sim_m16_flags=" -F ${sim_m16_filter} ${sim_m16_machine}" +sim_igen_flags="-F ${sim_igen_filter} ${sim_igen_machine} ${sim_igen_smp}" +sim_m16_flags=" -F ${sim_m16_filter} ${sim_m16_machine} ${sim_igen_smp}" AC_SUBST(sim_igen_flags) AC_SUBST(sim_m16_flags) diff --git a/sim/mips/interp.c b/sim/mips/interp.c index 889cc9c03dd..cc61dc68a69 100644 --- a/sim/mips/interp.c +++ b/sim/mips/interp.c @@ -79,6 +79,10 @@ char* pr_uword64 PARAMS ((uword64 addr)); #include "oengine.c" #undef SIM_MANIFESTS +/* Within interp.c we refer to the sim_state and sim_cpu directly. */ +#define SD sd +#define CPU cpu + /* The following reserved instruction value is used when a simulator trap is required. NOTE: Care must be taken, since this value may be @@ -156,6 +160,7 @@ mips_option_handler (sd, opt, arg) int opt; char *arg; { + int cpu_nr; switch (opt) { case OPTION_DINERO_TRACE: /* ??? */ @@ -164,20 +169,24 @@ mips_option_handler (sd, opt, arg) allow external control of the program points being traced (i.e. only from main onwards, excluding the run-time setup, etc.). */ - if (arg == NULL) - STATE |= simTRACE; - else if (strcmp (arg, "yes") == 0) - STATE |= simTRACE; - else if (strcmp (arg, "no") == 0) - STATE &= ~simTRACE; - else if (strcmp (arg, "on") == 0) - STATE |= simTRACE; - else if (strcmp (arg, "off") == 0) - STATE &= ~simTRACE; - else + for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++) { - fprintf (stderr, "Unreconized dinero-trace option `%s'\n", arg); - return SIM_RC_FAIL; + sim_cpu *cpu = STATE_CPU (sd, cpu_nr); + if (arg == NULL) + STATE |= simTRACE; + else if (strcmp (arg, "yes") == 0) + STATE |= simTRACE; + else if (strcmp (arg, "no") == 0) + STATE &= ~simTRACE; + else if (strcmp (arg, "on") == 0) + STATE |= simTRACE; + else if (strcmp (arg, "off") == 0) + STATE &= ~simTRACE; + else + { + fprintf (stderr, "Unreconized dinero-trace option `%s'\n", arg); + return SIM_RC_FAIL; + } } return SIM_RC_OK; #else /* !TRACE */ @@ -228,6 +237,7 @@ int interrupt_pending; static void interrupt_event (SIM_DESC sd, void *data) { + sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ if (SR & status_IE) { interrupt_pending = 0; @@ -251,7 +261,7 @@ sim_open (kind, cb, abfd, argv) char **argv; { SIM_DESC sd = sim_state_alloc (kind, cb); - sim_cpu *cpu = STATE_CPU (sd, 0); + sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); @@ -475,9 +485,10 @@ sim_close (sd, quitting) if (tracefh != NULL && tracefh != stderr) fclose(tracefh); tracefh = NULL; - STATE &= ~simTRACE; #endif /* TRACE */ + /* FIXME - free SD */ + return; } @@ -490,6 +501,7 @@ sim_write (sd,addr,buffer,size) int size; { int index; + sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ /* Return the number of bytes written, or zero if error. */ #ifdef DEBUG @@ -504,9 +516,9 @@ sim_write (sd,addr,buffer,size) address_word vaddr = (address_word)addr + index; address_word paddr; int cca; - if (!address_translation (sd, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW)) + if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW)) break; - if (sim_core_write_buffer (sd, NULL, sim_core_read_map, buffer + index, paddr, 1) != 1) + if (sim_core_write_buffer (SD, CPU, sim_core_read_map, buffer + index, paddr, 1) != 1) break; } @@ -521,6 +533,7 @@ sim_read (sd,addr,buffer,size) int size; { int index; + sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ /* Return the number of bytes read, or zero if error. */ #ifdef DEBUG @@ -532,9 +545,9 @@ sim_read (sd,addr,buffer,size) address_word vaddr = (address_word)addr + index; address_word paddr; int cca; - if (!address_translation (sd, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW)) + if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW)) break; - if (sim_core_read_buffer (sd, NULL, sim_core_read_map, buffer + index, paddr, 1) != 1) + if (sim_core_read_buffer (SD, CPU, sim_core_read_map, buffer + index, paddr, 1) != 1) break; } @@ -547,7 +560,7 @@ sim_store_register (sd,rn,memory) int rn; unsigned char *memory; { - sim_cpu *cpu = STATE_CPU (sd, 0); + sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ /* NOTE: gdb (the client) stores registers in target byte order while the simulator uses host byte order */ #ifdef DEBUG @@ -580,7 +593,7 @@ sim_fetch_register (sd,rn,memory) int rn; unsigned char *memory; { - sim_cpu *cpu = STATE_CPU (sd, 0); + sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */ /* NOTE: gdb (the client) stores registers in target byte order while the simulator uses host byte order */ #ifdef DEBUG @@ -657,8 +670,15 @@ sim_create_inferior (sd, abfd, argv,env) ColdReset(sd); if (abfd != NULL) - /* override PC value set by ColdReset () */ - PC = (unsigned64) bfd_get_start_address (abfd); + { + /* override PC value set by ColdReset () */ + int cpu_nr; + for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++) + { + sim_cpu *cpu = STATE_CPU (sd, cpu_nr); + CIA_SET (cpu, (unsigned64) bfd_get_start_address (abfd)); + } + } #if 0 /* def DEBUG */ if (argv || env) @@ -709,10 +729,10 @@ fetch_str (sd, addr) /* Simple monitor interface (currently setup for the IDT and PMON monitors) */ static void -sim_monitor(sd,cia,reason) - SIM_DESC sd; - address_word cia; - unsigned int reason; +sim_monitor (SIM_DESC sd, + sim_cpu *cpu, + address_word cia, + unsigned int reason) { #ifdef DEBUG printf("DBG: sim_monitor: entered (reason = %d)\n",reason); @@ -796,7 +816,7 @@ sim_monitor(sd,cia,reason) case 17: /* void _exit() */ { sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n"); - sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, sim_exited, + sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_exited, (unsigned int)(A0 & 0xFFFFFFFF)); break; } @@ -943,11 +963,11 @@ sim_monitor(sd,cia,reason) /* Store a word into memory. */ static void -store_word (sd, cia, vaddr, val) - SIM_DESC sd; - address_word cia; - uword64 vaddr; - t_reg val; +store_word (SIM_DESC sd, + sim_cpu *cpu, + address_word cia, + uword64 vaddr, + t_reg val) { address_word paddr; int uncached; @@ -975,10 +995,10 @@ store_word (sd, cia, vaddr, val) /* Load a word from memory. */ static t_reg -load_word (sd, cia, vaddr) - SIM_DESC sd; - address_word cia; - uword64 vaddr; +load_word (SIM_DESC sd, + sim_cpu *cpu, + address_word cia, + uword64 vaddr) { if ((vaddr & 3) != 0) SignalExceptionAddressLoad (); @@ -1012,9 +1032,10 @@ load_word (sd, cia, vaddr) code, but for ease of simulation we just handle them directly. */ static void -mips16_entry (sd,insn) - SIM_DESC sd; - unsigned int insn; +mips16_entry (SIM_DESC sd, + sim_cpu *cpu, + address_word cia, + unsigned int insn) { int aregs, sregs, rreg; @@ -1038,7 +1059,7 @@ mips16_entry (sd,insn) /* This is the entry pseudo-instruction. */ for (i = 0; i < aregs; i++) - store_word ((uword64) (SP + 4 * i), GPR[i + 4]); + store_word (SD, CPU, cia, (uword64) (SP + 4 * i), GPR[i + 4]); tsp = SP; SP -= 32; @@ -1046,13 +1067,13 @@ mips16_entry (sd,insn) if (rreg) { tsp -= 4; - store_word ((uword64) tsp, RA); + store_word (SD, CPU, cia, (uword64) tsp, RA); } for (i = 0; i < sregs; i++) { tsp -= 4; - store_word ((uword64) tsp, GPR[16 + i]); + store_word (SD, CPU, cia, (uword64) tsp, GPR[16 + i]); } } else @@ -1067,13 +1088,13 @@ mips16_entry (sd,insn) if (rreg) { tsp -= 4; - RA = load_word ((uword64) tsp); + RA = load_word (SD, CPU, cia, (uword64) tsp); } for (i = 0; i < sregs; i++) { tsp -= 4; - GPR[i + 16] = load_word ((uword64) tsp); + GPR[i + 16] = load_word (SD, CPU, cia, (uword64) tsp); } SP += 32; @@ -1137,7 +1158,13 @@ mips16_entry (sd,insn) void -dotrace (SIM_DESC sd,FILE *tracefh,int type,SIM_ADDR address,int width,char *comment,...) +dotrace (SIM_DESC sd, + sim_cpu *cpu, + FILE *tracefh, + int type, + SIM_ADDR address, + int width, + char *comment,...) { if (STATE & simTRACE) { va_list ap; @@ -1173,39 +1200,42 @@ dotrace (SIM_DESC sd,FILE *tracefh,int type,SIM_ADDR address,int width,char *com /*---------------------------------------------------------------------------*/ static void -ColdReset (sd) - SIM_DESC sd; +ColdReset (SIM_DESC sd) { - /* RESET: Fixed PC address: */ - PC = UNSIGNED64 (0xFFFFFFFFBFC00000); - /* The reset vector address is in the unmapped, uncached memory space. */ - - SR &= ~(status_SR | status_TS | status_RP); - SR |= (status_ERL | status_BEV); - - /* Cheat and allow access to the complete register set immediately */ - if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT - && WITH_TARGET_WORD_BITSIZE == 64) - SR |= status_FR; /* 64bit registers */ - - /* Ensure that any instructions with pending register updates are - cleared: */ - { - int loop; - for (loop = 0; (loop < PSLOTS); loop++) - PENDING_SLOT_REG[loop] = (LAST_EMBED_REGNUM + 1); - PENDING_IN = PENDING_OUT = PENDING_TOTAL = 0; - } - - /* Initialise the FPU registers to the unknown state */ - if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) + int cpu_nr; + for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++) { - int rn; - for (rn = 0; (rn < 32); rn++) - FPR_STATE[rn] = fmt_uninterpreted; + sim_cpu *cpu = STATE_CPU (sd, cpu_nr); + /* RESET: Fixed PC address: */ + PC = UNSIGNED64 (0xFFFFFFFFBFC00000); + /* The reset vector address is in the unmapped, uncached memory space. */ + + SR &= ~(status_SR | status_TS | status_RP); + SR |= (status_ERL | status_BEV); + + /* Cheat and allow access to the complete register set immediately */ + if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT + && WITH_TARGET_WORD_BITSIZE == 64) + SR |= status_FR; /* 64bit registers */ + + /* Ensure that any instructions with pending register updates are + cleared: */ + { + int loop; + for (loop = 0; (loop < PSLOTS); loop++) + PENDING_SLOT_REG[loop] = (LAST_EMBED_REGNUM + 1); + PENDING_IN = PENDING_OUT = PENDING_TOTAL = 0; + } + + /* Initialise the FPU registers to the unknown state */ + if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT) + { + int rn; + for (rn = 0; (rn < 32); rn++) + FPR_STATE[rn] = fmt_uninterpreted; + } + } - - return; } /* Description from page A-22 of the "MIPS IV Instruction Set" manual @@ -1227,15 +1257,15 @@ ColdReset (sd) function raises an exception and does not return. */ int -address_translation(sd,cia,vAddr,IorD,LorS,pAddr,CCA,raw) - SIM_DESC sd; - address_word cia; - address_word vAddr; - int IorD; - int LorS; - address_word *pAddr; - int *CCA; - int raw; +address_translation (SIM_DESC sd, + sim_cpu *cpu, + address_word cia, + address_word vAddr, + int IorD, + int LorS, + address_word *pAddr, + int *CCA, + int raw) { int res = -1; /* TRUE : Assume good return */ @@ -1263,14 +1293,14 @@ address_translation(sd,cia,vAddr,IorD,LorS,pAddr,CCA,raw) program, or alter architecturally-visible state. */ void -prefetch(sd,cia,CCA,pAddr,vAddr,DATA,hint) - SIM_DESC sd; - address_word cia; - int CCA; - address_word pAddr; - address_word vAddr; - int DATA; - int hint; +prefetch (SIM_DESC sd, + sim_cpu *cpu, + address_word cia, + int CCA, + address_word pAddr, + address_word vAddr, + int DATA, + int hint) { #ifdef DEBUG sim_io_printf(sd,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA,pr_addr(pAddr),pr_addr(vAddr),DATA,hint); @@ -1297,16 +1327,16 @@ prefetch(sd,cia,CCA,pAddr,vAddr,DATA,hint) satisfy a load reference. At a minimum, the block is the entire memory element. */ void -load_memory(sd,cia,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD) - SIM_DESC sd; - address_word cia; - uword64* memvalp; - uword64* memval1p; - int CCA; - int AccessLength; - address_word pAddr; - address_word vAddr; - int IorD; +load_memory (SIM_DESC sd, + sim_cpu *cpu, + address_word cia, + uword64* memvalp, + uword64* memval1p, + int CCA, + int AccessLength, + address_word pAddr, + address_word vAddr, + int IorD) { uword64 value = 0; uword64 value1 = 0; @@ -1337,7 +1367,7 @@ load_memory(sd,cia,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD) } #if defined(TRACE) - dotrace(sd,tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction")); + dotrace (SD, CPU, tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction")); #endif /* TRACE */ /* Read the specified number of bytes from memory. Adjust for @@ -1348,38 +1378,38 @@ load_memory(sd,cia,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD) { case AccessLength_QUADWORD : { - unsigned_16 val = sim_core_read_aligned_16 (STATE_CPU (sd, 0), NULL_CIA, + unsigned_16 val = sim_core_read_aligned_16 (cpu, NULL_CIA, sim_core_read_map, pAddr); value1 = VH8_16 (val); value = VL8_16 (val); break; } case AccessLength_DOUBLEWORD : - value = sim_core_read_aligned_8 (STATE_CPU (sd, 0), NULL_CIA, + value = sim_core_read_aligned_8 (cpu, NULL_CIA, sim_core_read_map, pAddr); break; case AccessLength_SEPTIBYTE : - value = sim_core_read_misaligned_7 (STATE_CPU (sd, 0), NULL_CIA, + value = sim_core_read_misaligned_7 (cpu, NULL_CIA, sim_core_read_map, pAddr); case AccessLength_SEXTIBYTE : - value = sim_core_read_misaligned_6 (STATE_CPU (sd, 0), NULL_CIA, + value = sim_core_read_misaligned_6 (cpu, NULL_CIA, sim_core_read_map, pAddr); case AccessLength_QUINTIBYTE : - value = sim_core_read_misaligned_5 (STATE_CPU (sd, 0), NULL_CIA, + value = sim_core_read_misaligned_5 (cpu, NULL_CIA, sim_core_read_map, pAddr); case AccessLength_WORD : - value = sim_core_read_aligned_4 (STATE_CPU (sd, 0), NULL_CIA, + value = sim_core_read_aligned_4 (cpu, NULL_CIA, sim_core_read_map, pAddr); break; case AccessLength_TRIPLEBYTE : - value = sim_core_read_misaligned_3 (STATE_CPU (sd, 0), NULL_CIA, + value = sim_core_read_misaligned_3 (cpu, NULL_CIA, sim_core_read_map, pAddr); case AccessLength_HALFWORD : - value = sim_core_read_aligned_2 (STATE_CPU (sd, 0), NULL_CIA, + value = sim_core_read_aligned_2 (cpu, NULL_CIA, sim_core_read_map, pAddr); break; case AccessLength_BYTE : - value = sim_core_read_aligned_1 (STATE_CPU (sd, 0), NULL_CIA, + value = sim_core_read_aligned_1 (cpu, NULL_CIA, sim_core_read_map, pAddr); break; default: @@ -1428,15 +1458,15 @@ load_memory(sd,cia,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD) will be changed. */ void -store_memory(sd,cia,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr) - SIM_DESC sd; - address_word cia; - int CCA; - int AccessLength; - uword64 MemElem; - uword64 MemElem1; /* High order 64 bits */ - address_word pAddr; - address_word vAddr; +store_memory (SIM_DESC sd, + sim_cpu *cpu, + address_word cia, + int CCA, + int AccessLength, + uword64 MemElem, + uword64 MemElem1, /* High order 64 bits */ + address_word pAddr, + address_word vAddr) { #ifdef DEBUG sim_io_printf(sd,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA,AccessLength,pr_uword64(MemElem),pr_uword64(MemElem1),pr_addr(pAddr),pr_addr(vAddr)); @@ -1451,7 +1481,7 @@ store_memory(sd,cia,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr) sim_io_error(sd,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength,(LOADDRMASK + 1)<<2,pr_addr(pAddr)); #if defined(TRACE) - dotrace(sd,tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store"); + dotrace (SD, CPU, tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store"); #endif /* TRACE */ #ifdef DEBUG @@ -1480,40 +1510,40 @@ store_memory(sd,cia,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr) case AccessLength_QUADWORD : { unsigned_16 val = U16_8 (MemElem1, MemElem); - sim_core_write_aligned_16 (STATE_CPU (sd, 0), NULL_CIA, + sim_core_write_aligned_16 (cpu, NULL_CIA, sim_core_write_map, pAddr, val); break; } case AccessLength_DOUBLEWORD : - sim_core_write_aligned_8 (STATE_CPU (sd, 0), NULL_CIA, + sim_core_write_aligned_8 (cpu, NULL_CIA, sim_core_write_map, pAddr, MemElem); break; case AccessLength_SEPTIBYTE : - sim_core_write_misaligned_7 (STATE_CPU (sd, 0), NULL_CIA, + sim_core_write_misaligned_7 (cpu, NULL_CIA, sim_core_write_map, pAddr, MemElem); break; case AccessLength_SEXTIBYTE : - sim_core_write_misaligned_6 (STATE_CPU (sd, 0), NULL_CIA, + sim_core_write_misaligned_6 (cpu, NULL_CIA, sim_core_write_map, pAddr, MemElem); break; case AccessLength_QUINTIBYTE : - sim_core_write_misaligned_5 (STATE_CPU (sd, 0), NULL_CIA, + sim_core_write_misaligned_5 (cpu, NULL_CIA, sim_core_write_map, pAddr, MemElem); break; case AccessLength_WORD : - sim_core_write_aligned_4 (STATE_CPU (sd, 0), NULL_CIA, + sim_core_write_aligned_4 (cpu, NULL_CIA, sim_core_write_map, pAddr, MemElem); break; case AccessLength_TRIPLEBYTE : - sim_core_write_misaligned_3 (STATE_CPU (sd, 0), NULL_CIA, + sim_core_write_misaligned_3 (cpu, NULL_CIA, sim_core_write_map, pAddr, MemElem); break; case AccessLength_HALFWORD : - sim_core_write_aligned_2 (STATE_CPU (sd, 0), NULL_CIA, + sim_core_write_aligned_2 (cpu, NULL_CIA, sim_core_write_map, pAddr, MemElem); break; case AccessLength_BYTE : - sim_core_write_aligned_1 (STATE_CPU (sd, 0), NULL_CIA, + sim_core_write_aligned_1 (cpu, NULL_CIA, sim_core_write_map, pAddr, MemElem); break; default: @@ -1526,6 +1556,7 @@ store_memory(sd,cia,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr) unsigned32 ifetch32 (SIM_DESC sd, + sim_cpu *cpu, address_word cia, address_word vaddr) { @@ -1552,10 +1583,10 @@ ifetch32 (SIM_DESC sd, loads and stores indicated by stype occur in the same order for all processors. */ void -sync_operation(sd,cia,stype) - SIM_DESC sd; - address_word cia; - int stype; +sync_operation (SIM_DESC sd, + sim_cpu *cpu, + address_word cia, + int stype) { #ifdef DEBUG sim_io_printf(sd,"SyncOperation(%d) : TODO\n",stype); @@ -1570,6 +1601,7 @@ sync_operation(sd,cia,stype) void signal_exception (SIM_DESC sd, + sim_cpu *cpu, address_word cia, int exception,...) { @@ -1627,7 +1659,7 @@ signal_exception (SIM_DESC sd, Debug |= Debug_DM; /* in debugging mode */ Debug |= Debug_DBp; /* raising a DBp exception */ PC = 0xBFC00200; - sim_engine_restart (sd, STATE_CPU (sd, 0), NULL, NULL_CIA); + sim_engine_restart (SD, CPU, NULL, NULL_CIA); } break; @@ -1649,11 +1681,11 @@ signal_exception (SIM_DESC sd, perform this magic. */ if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION) { - sim_monitor(sd, cia, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) ); + sim_monitor (SD, CPU, cia, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) ); /* NOTE: This assumes that a branch-and-link style instruction was used to enter the vector (which is the case with the current IDT monitor). */ - sim_engine_restart (sd, STATE_CPU (sd, 0), NULL, RA); + sim_engine_restart (SD, CPU, NULL, RA); } /* Look for the mips16 entry and exit instructions, and simulate a handler for them. */ @@ -1661,7 +1693,7 @@ signal_exception (SIM_DESC sd, && (instruction & 0xf81f) == 0xe809 && (instruction & 0x0c0) != 0x0c0) { - mips16_entry (instruction); + mips16_entry (SD, CPU, cia, instruction); sim_engine_restart (sd, NULL, NULL, NULL_CIA); } /* else fall through to normal exception processing */ @@ -1682,7 +1714,7 @@ signal_exception (SIM_DESC sd, va_end(ap); /* Check for our special terminating BREAK: */ if ((instruction & 0x03FFFFC0) == 0x03ff0000) { - sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, cia, + sim_engine_halt (SD, CPU, NULL, cia, sim_exited, (unsigned int)(A0 & 0xFFFFFFFF)); } } @@ -1690,7 +1722,7 @@ signal_exception (SIM_DESC sd, PC = cia - 4; /* reference the branch instruction */ else PC = cia; - sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, cia, + sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP); default: @@ -1745,35 +1777,35 @@ signal_exception (SIM_DESC sd, /* The following is so that the simulator will continue from the exception address on breakpoint operations. */ PC = EPC; - sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, + sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_stopped, SIM_SIGBUS); case ReservedInstruction: case CoProcessorUnusable: PC = EPC; - sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, + sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_stopped, SIM_SIGILL); case IntegerOverflow: case FPE: - sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, + sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_stopped, SIM_SIGFPE); case Trap: case Watch: case SystemCall: PC = EPC; - sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, + sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_stopped, SIM_SIGTRAP); case BreakPoint: PC = EPC; - sim_engine_abort (sd, STATE_CPU (sd, 0), NULL_CIA, + sim_engine_abort (SD, CPU, NULL_CIA, "FATAL: Should not encounter a breakpoint\n"); default : /* Unknown internal exception */ PC = EPC; - sim_engine_halt (sd, STATE_CPU (sd, 0), NULL, NULL_CIA, + sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_stopped, SIM_SIGABRT); } @@ -1785,7 +1817,7 @@ signal_exception (SIM_DESC sd, va_start(ap,exception); msg = va_arg(ap,char *); va_end(ap); - sim_engine_abort (sd, STATE_CPU (sd, 0), NULL_CIA, + sim_engine_abort (SD, CPU, NULL_CIA, "FATAL: Simulator error \"%s\"\n",msg); } } @@ -1817,13 +1849,13 @@ undefined_result(sd,cia) #endif /* WARN_RESULT */ void -cache_op(sd,cia,op,pAddr,vAddr,instruction) - SIM_DESC sd; - address_word cia; - int op; - address_word pAddr; - address_word vAddr; - unsigned int instruction; +cache_op (SIM_DESC sd, + sim_cpu *cpu, + address_word cia, + int op, + address_word pAddr, + address_word vAddr, + unsigned int instruction) { #if 1 /* stop warning message being displayed (we should really just remove the code) */ static int icache_warning = 1; @@ -1953,11 +1985,11 @@ cache_op(sd,cia,op,pAddr,vAddr,instruction) #endif /* DEBUG */ uword64 -value_fpr(sd,cia,fpr,fmt) - SIM_DESC sd; - address_word cia; - int fpr; - FP_formats fmt; +value_fpr (SIM_DESC sd, + sim_cpu *cpu, + address_word cia, + int fpr, + FP_formats fmt) { uword64 value = 0; int err = 0; @@ -2058,12 +2090,12 @@ value_fpr(sd,cia,fpr,fmt) } void -store_fpr(sd,cia,fpr,fmt,value) - SIM_DESC sd; - address_word cia; - int fpr; - FP_formats fmt; - uword64 value; +store_fpr (SIM_DESC sd, + sim_cpu *cpu, + address_word cia, + int fpr, + FP_formats fmt, + uword64 value) { int err = 0; @@ -2711,13 +2743,13 @@ SquareRoot(op,fmt) } uword64 -convert(sd,cia,rm,op,from,to) - SIM_DESC sd; - address_word cia; - int rm; - uword64 op; - FP_formats from; - FP_formats to; +convert (SIM_DESC sd, + sim_cpu *cpu, + address_word cia, + int rm, + uword64 op, + FP_formats from, + FP_formats to) { sim_fpu wop; sim_fpu_round round; @@ -2828,11 +2860,12 @@ CoProcPresent(coproc_number) } void -cop_lw(sd,cia,coproc_num,coproc_reg,memword) - SIM_DESC sd; - address_word cia; - int coproc_num, coproc_reg; - unsigned int memword; +cop_lw (SIM_DESC sd, + sim_cpu *cpu, + address_word cia, + int coproc_num, + int coproc_reg, + unsigned int memword) { switch (coproc_num) { #if defined(HASFPU) @@ -2856,11 +2889,12 @@ cop_lw(sd,cia,coproc_num,coproc_reg,memword) } void -cop_ld(sd,cia,coproc_num,coproc_reg,memword) - SIM_DESC sd; - address_word cia; - int coproc_num, coproc_reg; - uword64 memword; +cop_ld (SIM_DESC sd, + sim_cpu *cpu, + address_word cia, + int coproc_num, + int coproc_reg, + uword64 memword) { switch (coproc_num) { #if defined(HASFPU) @@ -2880,10 +2914,11 @@ cop_ld(sd,cia,coproc_num,coproc_reg,memword) } unsigned int -cop_sw(sd,cia,coproc_num,coproc_reg) - SIM_DESC sd; - address_word cia; - int coproc_num, coproc_reg; +cop_sw (SIM_DESC sd, + sim_cpu *cpu, + address_word cia, + int coproc_num, + int coproc_reg) { unsigned int value = 0; @@ -2922,10 +2957,11 @@ cop_sw(sd,cia,coproc_num,coproc_reg) } uword64 -cop_sd(sd,cia,coproc_num,coproc_reg) - SIM_DESC sd; - address_word cia; - int coproc_num, coproc_reg; +cop_sd (SIM_DESC sd, + sim_cpu *cpu, + address_word cia, + int coproc_num, + int coproc_reg) { uword64 value = 0; switch (coproc_num) { @@ -2957,10 +2993,10 @@ cop_sd(sd,cia,coproc_num,coproc_reg) } void -decode_coproc(sd,cia,instruction) - SIM_DESC sd; - address_word cia; - unsigned int instruction; +decode_coproc (SIM_DESC sd, + sim_cpu *cpu, + address_word cia, + unsigned int instruction) { int coprocnum = ((instruction >> 26) & 3); @@ -3130,6 +3166,7 @@ sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal) int nr_cpus; /* ignore */ int siggnal; /* ignore */ { + sim_cpu *cpu = STATE_CPU (sd, 0); /* hardwire to cpu 0 */ #if !defined(FASTSIM) unsigned int pipeline_count = 1; #endif diff --git a/sim/mips/mdmx.igen b/sim/mips/mdmx.igen index e9c2b85af58..9d2aca4a13e 100644 --- a/sim/mips/mdmx.igen +++ b/sim/mips/mdmx.igen @@ -47,11 +47,11 @@ return 1; case 3: /* bi word - ss011 */ - semantic_illegal (sd, cia); + semantic_illegal (CPU_, cia); return 2; case 7: /* long - ss111 */ - semantic_illegal (sd, cia); + semantic_illegal (CPU_, cia); return 3; default: abort (); @@ -74,8 +74,8 @@ case fmt_unknown: break; default: - sim_io_eprintf(sd, "Vector %d format invalid (PC = 0x%08lx)\n", - fpr, (long) cia); + sim_io_eprintf (SD, "Vector %d format invalid (PC = 0x%08lx)\n", + fpr, (long) CIA); FPR_STATE[fpr] = fmt_unknown; } switch (scale) @@ -107,8 +107,8 @@ case fmt_unknown: break; default: - sim_io_eprintf(sd, "Vector %d format invalid (PC = 0x%08lx)\n", - fpr, (long) cia); + sim_io_eprintf (SD, "Vector %d format invalid (PC = 0x%08lx)\n", + fpr, (long) cia); FPR_STATE[fpr] = fmt_unknown; } switch (scale) @@ -219,13 +219,12 @@ :function:::void:store_cc:int i, int value { - abort (); + SETFCC (i, value); } -:function:::int:fetch_cc:int i +:function:::int:value_cc:int i { - abort (); - return 0; + return GETFCC (i); } @@ -366,8 +365,8 @@ :function:::void:ByteAlign:int vd, int imm, int vs, int vt { int s = imm * 8; - unsigned64 rs = value_fpr (sd, cia, vs, fmt_long); - unsigned64 rt = value_fpr (sd, cia, vt, fmt_long); + unsigned64 rs = ValueFPR (vs, fmt_long); + unsigned64 rt = ValueFPR (vt, fmt_long); unsigned64 rd; if (BigEndianCPU) { @@ -387,7 +386,7 @@ rd = (MOVED64 (rs, s, 0, 63, 64 - s) | EXTRACTED64 (rt, 63, s)); } - store_fpr (sd, cia, vd, rd, fmt_long); + StoreFPR (vd, fmt_long, rd); } 010010,00,3.IMM,5.VT,5.VS,5.VD,0110,X,0::::ALNI.fmt @@ -743,7 +742,7 @@ int scale = get_scale (SD_, SEL); for (i = 0; i < (8 >> scale); i++) store_vr (SD_, scale, VD, i, - (fetch_cc (SD_, i) == 0 + (value_cc (SD_, i) == 0 ? value_vr (SD_, scale, VS, i) : select_vr (SD_, SEL, VT, i))); } @@ -763,7 +762,7 @@ int scale = get_scale (SD_, SEL); for (i = 0; i < (8 >> scale); i++) store_vr (SD_, scale, VD, i, - (fetch_cc (SD_, i) != 0 + (value_cc (SD_, i) != 0 ? value_vr (SD_, scale, VS, i) : select_vr (SD_, SEL, VT, i))); } diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h index 1f56c78655f..fdb023c4d83 100644 --- a/sim/mips/sim-main.h +++ b/sim/mips/sim-main.h @@ -93,11 +93,11 @@ typedef enum { fmt_uninterpreted_64 = 0x80000000, } FP_formats; -unsigned64 value_fpr PARAMS ((SIM_DESC sd, address_word cia, int fpr, FP_formats)); -#define ValueFPR(FPR,FMT) value_fpr (sd, cia, (FPR), (FMT)) +unsigned64 value_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats)); +#define ValueFPR(FPR,FMT) value_fpr (SD, CPU, cia, (FPR), (FMT)) -void store_fpr PARAMS ((SIM_DESC sd, address_word cia, int fpr, FP_formats fmt, unsigned64 value)); -#define StoreFPR(FPR,FMT,VALUE) store_fpr (sd, cia, (FPR), (FMT), (VALUE)) +void store_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats fmt, unsigned64 value)); +#define StoreFPR(FPR,FMT,VALUE) store_fpr (SD, CPU, cia, (FPR), (FMT), (VALUE)) int NaN PARAMS ((unsigned64 op, FP_formats fmt)); int Infinity PARAMS ((unsigned64 op, FP_formats fmt)); @@ -111,8 +111,9 @@ unsigned64 Multiply PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt)); unsigned64 Divide PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt)); unsigned64 Recip PARAMS ((unsigned64 op, FP_formats fmt)); unsigned64 SquareRoot PARAMS ((unsigned64 op, FP_formats fmt)); -unsigned64 convert PARAMS ((SIM_DESC sd, address_word cia, int rm, unsigned64 op, FP_formats from, FP_formats to)); -#define Convert(rm,op,from,to) convert(sd,cia,rm,op,from,to) +unsigned64 convert PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int rm, unsigned64 op, FP_formats from, FP_formats to)); +#define Convert(rm,op,from,to) \ +convert (SD, CPU, cia, rm, op, from, to) /* Macro to update FPSR condition-code field. This is complicated by the fact that there is a hole in the index range of the bits within @@ -292,7 +293,7 @@ struct _sim_cpu { #define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0) #define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA)) address_word dspc; /* delay-slot PC */ -#define DSPC ((STATE_CPU (sd,0))->dspc) +#define DSPC ((CPU)->dspc) /* Issue a delay slot instruction immediatly by re-calling idecode_issue */ @@ -300,18 +301,18 @@ struct _sim_cpu { do { \ address_word target = (TARGET); \ instruction_word delay_insn; \ - sim_events_slip (sd, 1); \ + sim_events_slip (SD, 1); \ CIA = CIA + 4; \ STATE |= simDELAYSLOT; \ delay_insn = IMEM (CIA); \ - idecode_issue (sd, delay_insn, (CIA)); \ + idecode_issue (CPU_, delay_insn, (CIA)); \ STATE &= ~simDELAYSLOT; \ NIA = target; \ } while (0) #define NULLIFY_NEXT_INSTRUCTION() \ do { \ - sim_events_slip (sd, 1); \ - dotrace (sd, tracefh, 2, NIA, 4, "load instruction"); \ + sim_events_slip (SD, 1); \ + dotrace (SD, CPU, tracefh, 2, NIA, 4, "load instruction"); \ NIA = CIA + 8; \ } while (0) @@ -320,8 +321,8 @@ struct _sim_cpu { /* State of the simulator */ unsigned int state; unsigned int dsstate; -#define STATE ((STATE_CPU (sd,0))->state) -#define DSSTATE ((STATE_CPU (sd,0))->dsstate) +#define STATE ((CPU)->state) +#define DSSTATE ((CPU)->dsstate) /* Flags in the "state" variable: */ #define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */ @@ -371,7 +372,7 @@ struct _sim_cpu { unsigned_word registers[LAST_EMBED_REGNUM + 1]; int register_widths[NUM_REGS]; -#define REGISTERS ((STATE_CPU (sd,0))->registers) +#define REGISTERS ((CPU)->registers) #define GPR (®ISTERS[0]) #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL)) @@ -395,7 +396,7 @@ struct _sim_cpu { #define COCIDX (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */ unsigned_word c0_config_reg; -#define C0_CONFIG ((STATE_CPU (sd,0))->c0_config_reg) +#define C0_CONFIG ((CPU)->c0_config_reg) /* The following are pseudonyms for standard registers */ #define ZERO (REGISTERS[0]) @@ -409,7 +410,7 @@ struct _sim_cpu { /* Keep the current format state for each register: */ FP_formats fpr_state[32]; -#define FPR_STATE ((STATE_CPU (sd, 0))->fpr_state) +#define FPR_STATE ((CPU)->fpr_state) /* Slots for delayed register updates. For the moment we just have a @@ -424,12 +425,12 @@ struct _sim_cpu { int pending_slot_count[PSLOTS]; int pending_slot_reg[PSLOTS]; unsigned_word pending_slot_value[PSLOTS]; -#define PENDING_IN ((STATE_CPU (sd, 0))->pending_in) -#define PENDING_OUT ((STATE_CPU (sd, 0))->pending_out) -#define PENDING_TOTAL ((STATE_CPU (sd, 0))->pending_total) -#define PENDING_SLOT_COUNT ((STATE_CPU (sd, 0))->pending_slot_count) -#define PENDING_SLOT_REG ((STATE_CPU (sd, 0))->pending_slot_reg) -#define PENDING_SLOT_VALUE ((STATE_CPU (sd, 0))->pending_slot_value) +#define PENDING_IN ((CPU)->pending_in) +#define PENDING_OUT ((CPU)->pending_out) +#define PENDING_TOTAL ((CPU)->pending_total) +#define PENDING_SLOT_COUNT ((CPU)->pending_slot_count) +#define PENDING_SLOT_REG ((CPU)->pending_slot_reg) +#define PENDING_SLOT_VALUE ((CPU)->pending_slot_value) /* The following are not used for MIPS IV onwards: */ #define PENDING_FILL(r,v) {\ @@ -455,7 +456,7 @@ struct _sim_cpu { no longer be atomic. In particular, it is cleared by exception return instructions. */ int llbit; -#define LLBIT ((STATE_CPU (sd, 0))->llbit) +#define LLBIT ((CPU)->llbit) /* The HIACCESS and LOACCESS counts are used to ensure that @@ -464,13 +465,13 @@ struct _sim_cpu { int hiaccess; int loaccess; -#define HIACCESS ((STATE_CPU (sd, 0))->hiaccess) -#define LOACCESS ((STATE_CPU (sd, 0))->loaccess) +#define HIACCESS ((CPU)->hiaccess) +#define LOACCESS ((CPU)->loaccess) /* start-sanitize-r5900 */ int hi1access; int lo1access; -#define HI1ACCESS ((STATE_CPU (sd, 0))->hi1access) -#define LO1ACCESS ((STATE_CPU (sd, 0))->lo1access) +#define HI1ACCESS ((CPU)->hi1access) +#define LO1ACCESS ((CPU)->lo1access) /* end-sanitize-r5900 */ #if 1 /* The 4300 and a few other processors have interlocks on hi/lo @@ -510,14 +511,14 @@ struct _sim_cpu { refers to the high 64 bits of that same register. */ signed_word registers1[LAST_EMBED_REGNUM + 1]; -#define REGISTERS1 ((STATE_CPU (sd, 0))->registers1) +#define REGISTERS1 ((CPU)->registers1) #define GPR1 (®ISTERS1[0]) #define LO1 (REGISTERS1[32]) #define HI1 (REGISTERS1[33]) #define REGISTER_SA (124) unsigned_word sa; /* the shift amount register */ -#define SA ((STATE_CPU (sd, 0))->sa) +#define SA ((CPU)->sa) /* end-sanitize-r5900 */ /* start-sanitize-vr5400 */ @@ -546,7 +547,7 @@ struct sim_state { struct swatch watch; - sim_cpu cpu[1]; + sim_cpu cpu[MAX_NR_PROCESSORS]; #if (WITH_SMP) #define STATE_CPU(sd,n) (&(sd)->cpu[n]) #else @@ -639,32 +640,37 @@ struct sim_state { run-time errors in the simulator. */ #define SimulatorFault (0xFFFFFFFF) -void signal_exception (SIM_DESC sd, address_word cia, int exception, ...); -#define SignalException(exc,instruction) signal_exception (sd, cia, (exc), (instruction)) -#define SignalExceptionInterrupt() signal_exception (sd, NULL_CIA, Interrupt) -#define SignalExceptionInstructionFetch() signal_exception (sd, cia, InstructionFetch) -#define SignalExceptionAddressStore() signal_exception (sd, cia, AddressStore) -#define SignalExceptionAddressLoad() signal_exception (sd, cia, AddressLoad) -#define SignalExceptionSimulatorFault(buf) signal_exception (sd, cia, SimulatorFault, buf) -#define SignalExceptionFPE() signal_exception (sd, cia, FPE) -#define SignalExceptionIntegerOverflow() signal_exception (sd, cia, IntegerOverflow) -#define SignalExceptionCoProcessorUnusable() signal_exception (sd, cia, CoProcessorUnusable) +void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...); +#define SignalException(exc,instruction) signal_exception (SD, CPU, cia, (exc), (instruction)) +#define SignalExceptionInterrupt() signal_exception (SD, CPU, NULL_CIA, Interrupt) +#define SignalExceptionInstructionFetch() signal_exception (SD, CPU, cia, InstructionFetch) +#define SignalExceptionAddressStore() signal_exception (SD, CPU, cia, AddressStore) +#define SignalExceptionAddressLoad() signal_exception (SD, CPU, cia, AddressLoad) +#define SignalExceptionSimulatorFault(buf) signal_exception (SD, CPU, cia, SimulatorFault, buf) +#define SignalExceptionFPE() signal_exception (SD, CPU, cia, FPE) +#define SignalExceptionIntegerOverflow() signal_exception (SD, CPU, cia, IntegerOverflow) +#define SignalExceptionCoProcessorUnusable() signal_exception (SD, CPU, cia, CoProcessorUnusable) /* Co-processor accesses */ -void cop_lw PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg, unsigned int memword)); -void cop_ld PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg, uword64 memword)); -unsigned int cop_sw PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg)); -uword64 cop_sd PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg)); +void cop_lw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword)); +void cop_ld PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword)); +unsigned int cop_sw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg)); +uword64 cop_sd PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg)); -#define COP_LW(coproc_num,coproc_reg,memword) cop_lw(sd,cia,coproc_num,coproc_reg,memword) -#define COP_LD(coproc_num,coproc_reg,memword) cop_ld(sd,cia,coproc_num,coproc_reg,memword) -#define COP_SW(coproc_num,coproc_reg) cop_sw(sd,cia,coproc_num,coproc_reg) -#define COP_SD(coproc_num,coproc_reg) cop_sd(sd,cia,coproc_num,coproc_reg) +#define COP_LW(coproc_num,coproc_reg,memword) \ +cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword) +#define COP_LD(coproc_num,coproc_reg,memword) \ +cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword) +#define COP_SW(coproc_num,coproc_reg) \ +cop_sw (SD, CPU, cia, coproc_num, coproc_reg) +#define COP_SD(coproc_num,coproc_reg) \ +cop_sd (SD, CPU, cia, coproc_num, coproc_reg) -void decode_coproc PARAMS ((SIM_DESC sd, address_word cia, unsigned int instruction)); -#define DecodeCoproc(instruction) decode_coproc(sd, cia, (instruction)) +void decode_coproc PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction)); +#define DecodeCoproc(instruction) \ +decode_coproc (SD, CPU, cia, (instruction)) @@ -701,31 +707,34 @@ void decode_coproc PARAMS ((SIM_DESC sd, address_word cia, unsigned int instruct #define AccessLength_DOUBLEWORD (7) #define AccessLength_QUADWORD (15) -int address_translation PARAMS ((SIM_DESC sd, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw)); +int address_translation PARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw)); #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \ -address_translation(sd,cia,vAddr,IorD,LorS,pAddr,CCA,raw) +address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw) -void load_memory PARAMS ((SIM_DESC sd, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, int AccessLength, address_word pAddr, address_word vAddr, int IorD)); +void load_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, int AccessLength, address_word pAddr, address_word vAddr, int IorD)); #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \ -load_memory(sd,cia,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD) +load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD) -void store_memory PARAMS ((SIM_DESC sd, address_word cia, int CCA, int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr)); +void store_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr)); #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \ -store_memory(sd,cia,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr) +store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr) -void cache_op PARAMS ((SIM_DESC sd, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction)); -#define CacheOp(op,pAddr,vAddr,instruction) cache_op(sd,cia,op,pAddr,vAddr,instruction) +void cache_op PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction)); +#define CacheOp(op,pAddr,vAddr,instruction) \ +cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction) -void sync_operation PARAMS ((SIM_DESC sd, address_word cia, int stype)); -#define SyncOperation(stype) sync_operation (sd, cia, (stype)) +void sync_operation PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype)); +#define SyncOperation(stype) \ +sync_operation (SD, CPU, cia, (stype)) -void prefetch PARAMS ((SIM_DESC sd, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint)); -#define Prefetch(CCA,pAddr,vAddr,DATA,hint) prefetch(sd,cia,CCA,pAddr,vAddr,DATA,hint) +void prefetch PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint)); +#define Prefetch(CCA,pAddr,vAddr,DATA,hint) \ +prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint) -unsigned32 ifetch32 PARAMS ((SIM_DESC sd, address_word cia, address_word vaddr)); -#define IMEM(CIA) ifetch32 (SD, (CIA), (CIA)) +unsigned32 ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr)); +#define IMEM(CIA) ifetch32 (SD, CPU, (CIA), (CIA)) -void dotrace PARAMS ((SIM_DESC sd, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...)); +void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...)); FILE *tracefh; #endif -- 2.30.2