From 0177ce64ff883f575ce9d37dad957f01bfad5759 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 14 Oct 2018 14:35:49 +0100 Subject: [PATCH] add category descriptions --- simple_v_extension/opcodes.mdwn | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/simple_v_extension/opcodes.mdwn b/simple_v_extension/opcodes.mdwn index 2241be015..c823fb9a0 100644 --- a/simple_v_extension/opcodes.mdwn +++ b/simple_v_extension/opcodes.mdwn @@ -4,7 +4,8 @@ Based on information from Michael Clark's riscv-meta opcodes table, this page categorises and identifies the type of parallelism that SimpleV indirectly adds on each RISC-V **standard** opcode. -* **-** no action +* **-** no change of behaviour takes place: operation remains + **completely scalar** even if it has registers. * **sv** - a standard contiguous (optionally predicated, optionally indirected) multi-register operation where the predication for the operation is taken from the **destination** register -- 2.30.2