From 019fd940055a8a81211a93e4f62af486d310962e Mon Sep 17 00:00:00 2001 From: "Gabriel L. Somlo" Date: Thu, 23 May 2019 16:27:17 -0400 Subject: [PATCH] fixup: generated-verilog submodule for experimental Rocket support FIXME: This patch uses https://github.com/gsomlo/rocket-litex-verilog, however in the long term it would perhaps be better if enjoy-digital hosted the generated-verilog repository. Once that's in place, I'd be happy to re-spin (and squash) this patch on top of its parent -- GLS --- .gitmodules | 3 +++ litex/soc/cores/cpu/rocket/verilog | 1 + 2 files changed, 4 insertions(+) create mode 160000 litex/soc/cores/cpu/rocket/verilog diff --git a/.gitmodules b/.gitmodules index d9db2754..706bd180 100644 --- a/.gitmodules +++ b/.gitmodules @@ -19,3 +19,6 @@ [submodule "litex/soc/cores/cpu/minerva/verilog"] path = litex/soc/cores/cpu/minerva/verilog url = http://github.com/enjoy-digital/minerva-verilog +[submodule "litex/soc/cores/cpu/rocket/verilog"] + path = litex/soc/cores/cpu/rocket/verilog + url = https://github.com/gsomlo/rocket-litex-verilog diff --git a/litex/soc/cores/cpu/rocket/verilog b/litex/soc/cores/cpu/rocket/verilog new file mode 160000 index 00000000..bcb12b02 --- /dev/null +++ b/litex/soc/cores/cpu/rocket/verilog @@ -0,0 +1 @@ +Subproject commit bcb12b0233b050dddef8d9c69bbf590d10428647 -- 2.30.2