From 01a1c19531e272d020a1716d97cc555e3b4fae6f Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Fri, 15 May 2020 18:55:55 -0400 Subject: [PATCH] Fix bug introduced when I made it possible to set the initial state of CR --- src/soc/alu/test/test_pipe_caller.py | 2 +- src/soc/logical/test/test_pipe_caller.py | 2 +- src/soc/shift_rot/test/test_pipe_caller.py | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/alu/test/test_pipe_caller.py b/src/soc/alu/test/test_pipe_caller.py index f9497c7c..d56019b2 100644 --- a/src/soc/alu/test/test_pipe_caller.py +++ b/src/soc/alu/test/test_pipe_caller.py @@ -200,7 +200,7 @@ class TestRunner(FHDLTestCase): print(test.name) program = test.program self.subTest(test.name) - simulator = ISA(pdecode2, test.regs, test.sprs) + simulator = ISA(pdecode2, test.regs, test.sprs, 0) gen = program.generate_instructions() instructions = list(zip(gen, program.assembly.splitlines())) diff --git a/src/soc/logical/test/test_pipe_caller.py b/src/soc/logical/test/test_pipe_caller.py index 82b62b06..190a9ade 100644 --- a/src/soc/logical/test/test_pipe_caller.py +++ b/src/soc/logical/test/test_pipe_caller.py @@ -202,7 +202,7 @@ class TestRunner(FHDLTestCase): print(test.name) program = test.program self.subTest(test.name) - simulator = ISA(pdecode2, test.regs, test.sprs) + simulator = ISA(pdecode2, test.regs, test.sprs, 0) gen = program.generate_instructions() instructions = list(zip(gen, program.assembly.splitlines())) diff --git a/src/soc/shift_rot/test/test_pipe_caller.py b/src/soc/shift_rot/test/test_pipe_caller.py index 97df2f20..3244332b 100644 --- a/src/soc/shift_rot/test/test_pipe_caller.py +++ b/src/soc/shift_rot/test/test_pipe_caller.py @@ -219,7 +219,7 @@ class TestRunner(FHDLTestCase): print(test.name) program = test.program self.subTest(test.name) - simulator = ISA(pdecode2, test.regs, test.sprs) + simulator = ISA(pdecode2, test.regs, test.sprs, 0) gen = program.generate_instructions() instructions = list(zip(gen, program.assembly.splitlines())) -- 2.30.2