From 01d13ffd8c34f585583be66846165be5b67c3656 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 10 Jul 2020 16:29:07 +0100 Subject: [PATCH] add random unsigned div tests --- src/soc/fu/div/test/test_pipe_caller.py | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py index 904cf30b..ba153112 100644 --- a/src/soc/fu/div/test/test_pipe_caller.py +++ b/src/soc/fu/div/test/test_pipe_caller.py @@ -171,6 +171,16 @@ class DIVTestCase(FHDLTestCase): initial_regs[2] = random.randint(0, (1<<64)-1) self.run_tst_program(Program(lst), initial_regs) + def test_rand_divwu(self): + insns = ["divwu", "divwu.", "divwuo", "divwuo."] + for i in range(40): + choice = random.choice(insns) + lst = [f"{choice} 3, 1, 2"] + initial_regs = [0] * 32 + initial_regs[1] = random.randint(0, (1<<64)-1) + initial_regs[2] = random.randint(0, (1<<64)-1) + self.run_tst_program(Program(lst), initial_regs) + def test_ilang(self): pspec = DIVPipeSpec(id_wid=2) alu = DIVBasePipe(pspec) -- 2.30.2