From 01efdc93a780e656c7f1204eac4ed8a03e4b68b1 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 19 Apr 2021 16:42:07 +0100 Subject: [PATCH] whoops correct links --- crypto_router_asic.mdwn | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/crypto_router_asic.mdwn b/crypto_router_asic.mdwn index 1cecf298c..880db24e0 100644 --- a/crypto_router_asic.mdwn +++ b/crypto_router_asic.mdwn @@ -12,13 +12,13 @@ All of these are entirely Libre-Licensed: OpenPOWER CPU with [[openpower/sv/bitmanip]] extensions * 180/130 nm (TBD) -* 5x [[shakhti/m_class/RGMII]] Gigabit Ethernet PHYs -* 2x USB [[shakhti/m_class/ULPI]] PHYs +* 5x [[shakti/m_class/RGMII]] Gigabit Ethernet PHYs +* 2x USB [[shakti/m_class/ULPI]] PHYs * Direct DMA interface (independent bulk transfer) * [JTAG](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/jtag.py;hb=HEAD), GPIO, I2C, PWM, UART, SPI, QSPI, SD/MMC * On-board Dual-ported SRAM (for Packet Buffers) -* Opencores [[shakhti/m_class/sdram]] +* Opencores [[shakti/m_class/sdram]] * Wishbone interfaces to all peripherals * [XICS ICP / ICS](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/interrupts/xics.py;hb=HEAD) Interrupt Controller -- 2.30.2