From 01f7947b568eb38ad122aa1e1435db4c04e03894 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 2 Jun 2020 13:44:23 +0200 Subject: [PATCH] targets: rename gateware-toolchain parameter to toolchain. --- litex/boards/targets/simple.py | 6 +++--- litex/boards/targets/ulx3s.py | 2 +- litex/boards/targets/versa_ecp5.py | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/litex/boards/targets/simple.py b/litex/boards/targets/simple.py index 70872bb0..0cc31be4 100755 --- a/litex/boards/targets/simple.py +++ b/litex/boards/targets/simple.py @@ -47,12 +47,12 @@ def main(): soc_core_args(parser) parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("platform", help="Module name of the platform to build for") - parser.add_argument("--gateware-toolchain", default=None, help="FPGA gateware toolchain used for build") + parser.add_argument("--toolchain", default=None, help="FPGA gateware toolchain used for build") args = parser.parse_args() platform_module = importlib.import_module(args.platform) - if args.gateware_toolchain is not None: - platform = platform_module.Platform(toolchain=args.gateware_toolchain) + if args.toolchain is not None: + platform = platform_module.Platform(toolchain=args.toolchain) else: platform = platform_module.Platform() soc = BaseSoC(platform, with_ethernet=args.with_ethernet, **soc_core_argdict(args)) diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py index 20ae17d3..fbc00802 100755 --- a/litex/boards/targets/ulx3s.py +++ b/litex/boards/targets/ulx3s.py @@ -102,7 +102,7 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on ULX3S") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") + parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") parser.add_argument("--device", dest="device", default="LFE5U-45F", help="FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F") parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default=50MHz)") parser.add_argument("--sdram-module", default="MT48LC16M16", help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)") diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py index e07f60e3..aacbf5c2 100755 --- a/litex/boards/targets/versa_ecp5.py +++ b/litex/boards/targets/versa_ecp5.py @@ -119,7 +119,7 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Versa ECP5") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") + parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") builder_args(parser) soc_sdram_args(parser) trellis_args(parser) -- 2.30.2