From 020fffcb5859be5afbbcecc2462a94da31c8117a Mon Sep 17 00:00:00 2001 From: =?utf8?q?Jean-Fran=C3=A7ois=20Nguyen?= Date: Mon, 28 Jun 2021 16:19:13 +0200 Subject: [PATCH] periph.serial: update default rx_depth value to 256. This is allows the RX FIFO to buffer a complete SFL frame, to avoid a race condition during a serialboot at a high baudrate. --- lambdasoc/periph/serial.py | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/lambdasoc/periph/serial.py b/lambdasoc/periph/serial.py index a25c78d..cd7974b 100644 --- a/lambdasoc/periph/serial.py +++ b/lambdasoc/periph/serial.py @@ -14,6 +14,13 @@ class AsyncSerialPeripheral(Peripheral, Elaboratable): See :class:`nmigen_stdio.serial.AsyncSerial` for details. + Notes + ----- + + * If this peripheral is used with the LambdaSoC BIOS, `rx_depth * data_bits` should be at least + 256 bytes in order to buffer a complete SFL frame. Otherwise, a race condition may occur during + a serialboot at high baudrates. + CSR registers ------------- divisor : read/write @@ -62,7 +69,7 @@ class AsyncSerialPeripheral(Peripheral, Elaboratable): irq : :class:`IRQLine` Interrupt request line. """ - def __init__(self, *, rx_depth=16, tx_depth=16, **kwargs): + def __init__(self, *, rx_depth=256, tx_depth=16, data_bits=8, **kwargs): super().__init__() self._phy = AsyncSerial(data_bits=data_bits, **kwargs) -- 2.30.2