From 02669870b503ce4832c9343bf17fce579ec49daf Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 11 Oct 2020 14:57:38 +0100 Subject: [PATCH] comment out XICS/GPIO interrupt test, causes ECP5 litex build to fail (input incorrectly detected as output) --- src/soc/simple/issuer.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index 7fb102fb..aafae394 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -140,8 +140,10 @@ class TestIssuerInternal(Elaboratable): m.submodules.simple_gpio = simple_gpio = self.simple_gpio # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl) - if self.gpio and self.xics: - comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0]) + # XXX causes litex ECP5 test to get wrong idea about input and output + # (but works with verilator sim *sigh*) + #if self.gpio and self.xics: + # comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0]) # instruction decoder pdecode = create_pdecode() -- 2.30.2