From 026b6f5ac2f9be2bac86f7c996a49b61d57b0c69 Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 20 May 2022 23:16:59 +0100 Subject: [PATCH] --- openpower/sv/bitmanip.mdwn | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn index 04c671e55..d2c888504 100644 --- a/openpower/sv/bitmanip.mdwn +++ b/openpower/sv/bitmanip.mdwn @@ -97,7 +97,7 @@ TODO: convert all instructions to use RT and not RS | NN | RT | RA |itype/| im0-4 | im5-7 00 |0 | xpermi | TLI-Form | | NN | RT | RA | RB | RC | nh 00 00 |1 | binlut | VA-Form | | NN | RT | RA | RB | /BFA/ | 0 01 00 |1 | bincrflut | VA-Form | -| NN | RT | RA | RB | RC | 1 01 00 |1 | grevlogr | VA-Form | +| NN | | | | | 1 01 00 |1 | rsvd | | | NN | | | | | - 10 00 |1 | rsvd | | | NN | | | | | 0 11 00 |1 | svshape | SVM-Form | | NN | | | | | 1 11 00 |1 | svremap | SVRM-Form | @@ -133,7 +133,7 @@ the [[sv/av_opcodes]]) | NN | RT | RA | RB | 1 | 00 | 1001 110 |Rc| av abss | X-Form | | NN | RT | RA | RB | 1 | 01 | 1001 110 |Rc| av absu | X-Form | | NN | RT | RA | RB | 1 | 10 | 1001 110 |Rc| av avgadd | X-Form | -| NN | | | | 1 | 11 | 1001 110 |Rc| rsvd | | +| NN | RT | RA | RB | 1 | 11 | 1001 110 |Rc| grevlutr | X-Form | | NN | RT | RA | RB | 0 | itype | 1101 110 |Rc| shadd | X-Form | | NN | RT | RA | RB | 1 | itype | 1101 110 |Rc| shadduw | X-Form | | NN | RT | RA | RB | 0 | 00 | 0010 110 |Rc| gorc | X-Form | @@ -501,20 +501,22 @@ uint64_t grevlut(uint64_t RA, uint64_t RB, uint8 imm, bool iv, bool is32b) } ``` -A 3-register variant may specify different LUT-pairs per row, -using one byte of RC for each. +A variant may specify different LUT-pairs per row, +using one byte of RB for each. If it is desired that +a particular row-crossover shall not be applied it is +a simple matter to set the appropriate LUT-pair in RB +to effect an identity transform for that row (`0b11001010`). ``` -uint64_t grevlutr(uint64_t RA, uint64_t RB, uint64_t RC, bool iv, bool is32b) +uint64_t grevlutr(uint64_t RA, uint64_t RB, bool iv, bool is32b) { uint64_t x = 0x5555_5555_5555_5555; if (RA != 0) x = GPR(RA); if (iv) x = ~x; - int shamt = RB & 31 if is32b else 63 for i in 0 to (6-is32b) step = 1<>(i*8))&0xff - if (shamt & step) x = dorow(imm, x, step, is32b) + imm = (RB>>(i*8))&0xff + x = dorow(imm, x, step, is32b) return x; } -- 2.30.2