From 02745afd3f733b0bc00846f98199a346a83358da Mon Sep 17 00:00:00 2001 From: Timothy Hayes Date: Fri, 10 Jan 2020 18:03:22 +0000 Subject: [PATCH] cpu: Add HTM ThreadContext API JIRA: https://gem5.atlassian.net/browse/GEM5-587 Change-Id: I9d60f69592c8072e70cef18787b5a4f2fc737a9d Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30324 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- src/cpu/checker/thread_context.hh | 22 +++++++++++++++++++++- src/cpu/o3/thread_context.hh | 8 +++++++- src/cpu/o3/thread_context_impl.hh | 25 ++++++++++++++++++++++++- src/cpu/simple_thread.cc | 22 +++++++++++++++++++++- src/cpu/simple_thread.hh | 11 ++++++++++- src/cpu/thread_context.hh | 8 +++++++- 6 files changed, 90 insertions(+), 6 deletions(-) diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh index e98b3a221..b5a974bce 100644 --- a/src/cpu/checker/thread_context.hh +++ b/src/cpu/checker/thread_context.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2012, 2016-2018 ARM Limited + * Copyright (c) 2011-2012, 2016-2018, 2020 ARM Limited * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * @@ -554,6 +554,26 @@ class CheckerThreadContext : public ThreadContext { actualTC->setCCRegFlat(idx, val); } + + // hardware transactional memory + void + htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override + { + panic("function not implemented"); + } + + BaseHTMCheckpointPtr& + getHtmCheckpointPtr() override + { + panic("function not implemented"); + } + + void + setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override + { + panic("function not implemented"); + } + }; #endif // __CPU_CHECKER_EXEC_CONTEXT_HH__ diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index e3e11fe18..b3eba134d 100644 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2012, 2016-2018 ARM Limited + * Copyright (c) 2011-2012, 2016-2018, 2020 ARM Limited * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * @@ -479,6 +479,12 @@ class O3ThreadContext : public ThreadContext RegVal readCCRegFlat(RegIndex idx) const override; void setCCRegFlat(RegIndex idx, RegVal val) override; + + // hardware transactional memory + void htmAbortTransaction(uint64_t htm_uid, + HtmFailureFaultCause cause) override; + BaseHTMCheckpointPtr& getHtmCheckpointPtr() override; + void setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override; }; #endif diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index a5db7641c..014b0f588 100644 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2012, 2016-2017 ARM Limited + * Copyright (c) 2010-2012, 2016-2017, 2019 ARM Limited * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * @@ -325,4 +325,27 @@ O3ThreadContext::setMiscReg(RegIndex misc_reg, RegVal val) conditionalSquash(); } +// hardware transactional memory +template +void +O3ThreadContext::htmAbortTransaction(uint64_t htmUid, + HtmFailureFaultCause cause) +{ + panic("function not implemented\n"); +} + +template +BaseHTMCheckpointPtr& +O3ThreadContext::getHtmCheckpointPtr() +{ + panic("function not implemented\n"); +} + +template +void +O3ThreadContext::setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) +{ + panic("function not implemented\n"); +} + #endif //__CPU_O3_THREAD_CONTEXT_IMPL_HH__ diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc index 14551fbab..b0ffc8264 100644 --- a/src/cpu/simple_thread.cc +++ b/src/cpu/simple_thread.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 ARM Limited + * Copyright (c) 2018, 2020 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -50,6 +50,7 @@ #include "base/trace.hh" #include "config/the_isa.hh" #include "cpu/base.hh" +#include "cpu/simple/base.hh" #include "cpu/thread_context.hh" #include "mem/se_translating_port_proxy.hh" #include "mem/translating_port_proxy.hh" @@ -169,3 +170,22 @@ SimpleThread::copyArchRegs(ThreadContext *src_tc) { TheISA::copyRegs(src_tc, this); } + +// hardware transactional memory +void +SimpleThread::htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) +{ + panic("function not implemented\n"); +} + +BaseHTMCheckpointPtr& +SimpleThread::getHtmCheckpointPtr() +{ + panic("function not implemented\n"); +} + +void +SimpleThread::setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) +{ + panic("function not implemented\n"); +} diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index 2c785736b..eb8810459 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2012, 2016-2018 ARM Limited + * Copyright (c) 2011-2012, 2016-2018, 2020 ARM Limited * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * @@ -45,6 +45,7 @@ #include #include "arch/decoder.hh" +#include "arch/generic/htm.hh" #include "arch/generic/tlb.hh" #include "arch/isa.hh" #include "arch/registers.hh" @@ -58,6 +59,7 @@ #include "debug/IntRegs.hh" #include "debug/VecPredRegs.hh" #include "debug/VecRegs.hh" +#include "mem/htm.hh" #include "mem/page_table.hh" #include "mem/request.hh" #include "sim/byteswap.hh" @@ -661,6 +663,13 @@ class SimpleThread : public ThreadState, public ThreadContext RegVal readCCRegFlat(RegIndex idx) const override { return ccRegs[idx]; } void setCCRegFlat(RegIndex idx, RegVal val) override { ccRegs[idx] = val; } + + // hardware transactional memory + void htmAbortTransaction(uint64_t htm_uid, + HtmFailureFaultCause cause) override; + + BaseHTMCheckpointPtr& getHtmCheckpointPtr() override; + void setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override; }; diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index 6662502f0..c4fbaf405 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2012, 2016-2018 ARM Limited + * Copyright (c) 2011-2012, 2016-2018, 2020 ARM Limited * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * @@ -45,6 +45,7 @@ #include #include +#include "arch/generic/htm.hh" #include "arch/generic/isa.hh" #include "arch/registers.hh" #include "arch/types.hh" @@ -340,6 +341,11 @@ class ThreadContext : public PCEventScope virtual void setCCRegFlat(RegIndex idx, RegVal val) = 0; /** @} */ + // hardware transactional memory + virtual void htmAbortTransaction(uint64_t htm_uid, + HtmFailureFaultCause cause) = 0; + virtual BaseHTMCheckpointPtr& getHtmCheckpointPtr() = 0; + virtual void setHtmCheckpointPtr(BaseHTMCheckpointPtr cpt) = 0; }; /** @{ */ -- 2.30.2